JPS5459969A - Electronic type timing device - Google Patents

Electronic type timing device

Info

Publication number
JPS5459969A
JPS5459969A JP12606877A JP12606877A JPS5459969A JP S5459969 A JPS5459969 A JP S5459969A JP 12606877 A JP12606877 A JP 12606877A JP 12606877 A JP12606877 A JP 12606877A JP S5459969 A JPS5459969 A JP S5459969A
Authority
JP
Japan
Prior art keywords
time
time limit
memory
limit setting
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12606877A
Other languages
Japanese (ja)
Inventor
Takayasu Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12606877A priority Critical patent/JPS5459969A/en
Publication of JPS5459969A publication Critical patent/JPS5459969A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

PURPOSE: To perform time limit setting of program time operation freely and improve operating characteristic by providing a clocking circuit and plural time limit setting memories.
CONSTITUTION: A random access memory 53 which is provided with time limit setting memories 531 thru 539, an inputting memory 540, a time setting memory 541 and a controlling memory 542 is provided to a microcomputer 13, to which are then incorporated a clocking circuit 47, a setting memory 48, a comparator 49, a down counter 50, a cycle operation priority circuit 51 and an alarm counter 52. Then, a central control circuit 45 controls the random access memory 53 based on the programs having been set in the ROM 46 and sets the time limit information of the time in the time limit setting memories 531 thru 539, whereby the time limit setting of the program time operation may be accomplished freely at minimum effective time intervals
COPYRIGHT: (C)1979,JPO&Japio
JP12606877A 1977-10-20 1977-10-20 Electronic type timing device Pending JPS5459969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12606877A JPS5459969A (en) 1977-10-20 1977-10-20 Electronic type timing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12606877A JPS5459969A (en) 1977-10-20 1977-10-20 Electronic type timing device

Publications (1)

Publication Number Publication Date
JPS5459969A true JPS5459969A (en) 1979-05-15

Family

ID=14925813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12606877A Pending JPS5459969A (en) 1977-10-20 1977-10-20 Electronic type timing device

Country Status (1)

Country Link
JP (1) JPS5459969A (en)

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