JPS546429A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS546429A
JPS546429A JP7148277A JP7148277A JPS546429A JP S546429 A JPS546429 A JP S546429A JP 7148277 A JP7148277 A JP 7148277A JP 7148277 A JP7148277 A JP 7148277A JP S546429 A JPS546429 A JP S546429A
Authority
JP
Japan
Prior art keywords
memory device
semiconductor memory
input time
input
multiplexes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7148277A
Other languages
Japanese (ja)
Other versions
JPS6215947B2 (en
Inventor
Tetsuya Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7148277A priority Critical patent/JPS546429A/en
Publication of JPS546429A publication Critical patent/JPS546429A/en
Publication of JPS6215947B2 publication Critical patent/JPS6215947B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To control various operation modes with a small number of terminals, by providing an input circuit which multiplexes a latch signal having assigned the input time of data and a strobe signal which can select the input time from the outside freely to a certain degree.
JP7148277A 1977-06-16 1977-06-16 Semiconductor memory device Granted JPS546429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7148277A JPS546429A (en) 1977-06-16 1977-06-16 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7148277A JPS546429A (en) 1977-06-16 1977-06-16 Semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS546429A true JPS546429A (en) 1979-01-18
JPS6215947B2 JPS6215947B2 (en) 1987-04-09

Family

ID=13461894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7148277A Granted JPS546429A (en) 1977-06-16 1977-06-16 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS546429A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602356A (en) * 1981-12-02 1986-07-22 Fujitsu Limited Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602356A (en) * 1981-12-02 1986-07-22 Fujitsu Limited Semiconductor memory device

Also Published As

Publication number Publication date
JPS6215947B2 (en) 1987-04-09

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