JPS5464433A - Memory cell - Google Patents

Memory cell

Info

Publication number
JPS5464433A
JPS5464433A JP13106577A JP13106577A JPS5464433A JP S5464433 A JPS5464433 A JP S5464433A JP 13106577 A JP13106577 A JP 13106577A JP 13106577 A JP13106577 A JP 13106577A JP S5464433 A JPS5464433 A JP S5464433A
Authority
JP
Japan
Prior art keywords
cmos
memory cell
drain
source
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13106577A
Other languages
Japanese (ja)
Inventor
Michitoku Kamatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13106577A priority Critical patent/JPS5464433A/en
Publication of JPS5464433A publication Critical patent/JPS5464433A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: To establish memory cell small in static capacitance and easy for sense amplifier constitution, by applying a voltage close to the threshold value of the transistor to the decoder line and by operating the high resistance load for CMOS, when the memory circuit is inoperative, in RAM using CMOS.
CONSTITUTION: The first potential Vcc is applied after connecting the source and drain of the first and second CMOS TP1 and TP2 of equal conduction type commonly, and the gate, drain or source electrode of CMOS TP1 and TP2 is in cross connection. The junctions 3, 4 in cross connection are connected to the X decoder line 1 of the gate electrode, and the source 1 is connected to the drain of CMOSTn1 and Tn2 connected to the 1 bit line 2 and 0 bit line 6, constituting the memory cell. Further, the memory cell is read out or written in by taking the chip into active state when the enable CE is at high level, and the memory content is stored by taking the chip to storage state when it is at low level.
COPYRIGHT: (C)1979,JPO&Japio
JP13106577A 1977-10-31 1977-10-31 Memory cell Pending JPS5464433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13106577A JPS5464433A (en) 1977-10-31 1977-10-31 Memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13106577A JPS5464433A (en) 1977-10-31 1977-10-31 Memory cell

Publications (1)

Publication Number Publication Date
JPS5464433A true JPS5464433A (en) 1979-05-24

Family

ID=15049176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13106577A Pending JPS5464433A (en) 1977-10-31 1977-10-31 Memory cell

Country Status (1)

Country Link
JP (1) JPS5464433A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093176A (en) * 2000-07-10 2002-03-29 Mitsubishi Electric Corp Storage device
JP2011165313A (en) * 2000-07-10 2011-08-25 Renesas Electronics Corp Memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093176A (en) * 2000-07-10 2002-03-29 Mitsubishi Electric Corp Storage device
JP2011165313A (en) * 2000-07-10 2011-08-25 Renesas Electronics Corp Memory device

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