JPS5465403A - Reception time correcting circuit - Google Patents

Reception time correcting circuit

Info

Publication number
JPS5465403A
JPS5465403A JP13236377A JP13236377A JPS5465403A JP S5465403 A JPS5465403 A JP S5465403A JP 13236377 A JP13236377 A JP 13236377A JP 13236377 A JP13236377 A JP 13236377A JP S5465403 A JPS5465403 A JP S5465403A
Authority
JP
Japan
Prior art keywords
time
signal
circuit
lead
reception time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13236377A
Other languages
Japanese (ja)
Other versions
JPS5747868B2 (en
Inventor
Koichi Murata
Takao Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NTT Inc
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13236377A priority Critical patent/JPS5465403A/en
Publication of JPS5465403A publication Critical patent/JPS5465403A/en
Publication of JPS5747868B2 publication Critical patent/JPS5747868B2/ja
Granted legal-status Critical Current

Links

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  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To ensure the normal reception of the parallel signal received the jitter through the transmission line by correcting the signals which has a change between the signal time and the non-signal time in the receiving device featuring the reception answer delay.
CONSTITUTION: The parallel signals of signal time TA and non-signal time nTA receive the jitter via the transmission line and emerges at information lead 1. With set of FF10 corresponding to lead 1, the output is sent to receiving device 15 within set time Tm of circuit 12. At the end of transmission to device 15, FF10 is reset by circuit 13, At the same time, the set of FF10 is inhibited via circuit 11 during the period from the transmission start to device 15 through time Tm+Tn. And FF10 is set by circuit 4 if the signal emerges at lead 1 while the set of FF10 is not inhibited. Thus, the corrected signal is transmitted to device 15 during time Tm.
COPYRIGHT: (C)1979,JPO&Japio
JP13236377A 1977-11-02 1977-11-02 Reception time correcting circuit Granted JPS5465403A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13236377A JPS5465403A (en) 1977-11-02 1977-11-02 Reception time correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13236377A JPS5465403A (en) 1977-11-02 1977-11-02 Reception time correcting circuit

Publications (2)

Publication Number Publication Date
JPS5465403A true JPS5465403A (en) 1979-05-26
JPS5747868B2 JPS5747868B2 (en) 1982-10-13

Family

ID=15079606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13236377A Granted JPS5465403A (en) 1977-11-02 1977-11-02 Reception time correcting circuit

Country Status (1)

Country Link
JP (1) JPS5465403A (en)

Also Published As

Publication number Publication date
JPS5747868B2 (en) 1982-10-13

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