JPS5466014A - Multiple converter - Google Patents

Multiple converter

Info

Publication number
JPS5466014A
JPS5466014A JP13318177A JP13318177A JPS5466014A JP S5466014 A JPS5466014 A JP S5466014A JP 13318177 A JP13318177 A JP 13318177A JP 13318177 A JP13318177 A JP 13318177A JP S5466014 A JPS5466014 A JP S5466014A
Authority
JP
Japan
Prior art keywords
group
signal
multiplication
work memory
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13318177A
Other languages
Japanese (ja)
Other versions
JPS5650461B2 (en
Inventor
Yoichi Sakai
Masahiro Ko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13318177A priority Critical patent/JPS5466014A/en
Publication of JPS5466014A publication Critical patent/JPS5466014A/en
Publication of JPS5650461B2 publication Critical patent/JPS5650461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To use a circuit efficiently by attaining the frame-synchronism detection, synchronization, and higher-group word multiplication of each lower-group signal by using a work memory and common arithmetic circit. CONSTITUTION:At the time of the synchronous multiplication of a lower-group time-division multiple signal, fram counter regions consisting of a bit counter for word synchronization of a lower-group signal in a bit-multiplication signal and a time slot counter indicating the channel number in each lower-group signal are arranged as one word for each lower group in work memory 18. Common arithmetic circuit 17, on the other hand, attains the detection frame-synchronous bits, decision of information bits, write control of each work memory region for each lower- group signal in common. In this way, the frame-synchronism detection, synchronization, and higher-group word multiplication of each lower-group signal are performed by work memory 15 and common arithmetic circuit 17, so that the circuit can be used efficiently.
JP13318177A 1977-11-07 1977-11-07 Multiple converter Granted JPS5466014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13318177A JPS5466014A (en) 1977-11-07 1977-11-07 Multiple converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13318177A JPS5466014A (en) 1977-11-07 1977-11-07 Multiple converter

Publications (2)

Publication Number Publication Date
JPS5466014A true JPS5466014A (en) 1979-05-28
JPS5650461B2 JPS5650461B2 (en) 1981-11-28

Family

ID=15098567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13318177A Granted JPS5466014A (en) 1977-11-07 1977-11-07 Multiple converter

Country Status (1)

Country Link
JP (1) JPS5466014A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214652A (en) * 1984-04-11 1985-10-26 Nec Corp Speed converting circuit
JPH03247038A (en) * 1990-02-26 1991-11-05 Nec Corp Multiplex system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214652A (en) * 1984-04-11 1985-10-26 Nec Corp Speed converting circuit
JPH03247038A (en) * 1990-02-26 1991-11-05 Nec Corp Multiplex system

Also Published As

Publication number Publication date
JPS5650461B2 (en) 1981-11-28

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