JPS5467731A - Address buffer circuit - Google Patents

Address buffer circuit

Info

Publication number
JPS5467731A
JPS5467731A JP13499877A JP13499877A JPS5467731A JP S5467731 A JPS5467731 A JP S5467731A JP 13499877 A JP13499877 A JP 13499877A JP 13499877 A JP13499877 A JP 13499877A JP S5467731 A JPS5467731 A JP S5467731A
Authority
JP
Japan
Prior art keywords
becomes
node
case
timing signal
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13499877A
Other languages
Japanese (ja)
Other versions
JPS5938671B2 (en
Inventor
Tadaaki Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP52134998A priority Critical patent/JPS5938671B2/en
Publication of JPS5467731A publication Critical patent/JPS5467731A/en
Publication of JPS5938671B2 publication Critical patent/JPS5938671B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To make this circuit low-power consumption by eliminating the unbalance of the output part and giving a ratioless constitution to the circuit by giving a bisymmetrical constitution to this address buffer circuit. CONSTITUTION:Timing signal theta1 is ''1''-level, and transistors 27 and 28 are turned on, and nodes 214 and 215 are pre-charged. By timing signal theta2=1, transistors 24 and 25 are turned on to transmit address input A1I to node 212. In case that A1I is ''1'', node 211 becomes Vref. In case of A1I=O, node 211 become zero potential. When timing signal theta3 becomes ''1'', node 212 becomes ''O'' in case of A1I=1. When either of nodes 212 and 213 becomes below Vth and theta4 becomes ''1'' node 214 has electric charge discharged and becomes ''O''. When timing signal theta5 becomes ''1'', the output becomes ''1'' in case of node 214=1, and A10 becomes ''1'' in case of 215=1.
JP52134998A 1977-11-10 1977-11-10 address buffer circuit Expired JPS5938671B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52134998A JPS5938671B2 (en) 1977-11-10 1977-11-10 address buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52134998A JPS5938671B2 (en) 1977-11-10 1977-11-10 address buffer circuit

Publications (2)

Publication Number Publication Date
JPS5467731A true JPS5467731A (en) 1979-05-31
JPS5938671B2 JPS5938671B2 (en) 1984-09-18

Family

ID=15141539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52134998A Expired JPS5938671B2 (en) 1977-11-10 1977-11-10 address buffer circuit

Country Status (1)

Country Link
JP (1) JPS5938671B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812194A (en) * 1981-07-15 1983-01-24 Oki Electric Ind Co Ltd Latching circuit of address input signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812194A (en) * 1981-07-15 1983-01-24 Oki Electric Ind Co Ltd Latching circuit of address input signal

Also Published As

Publication number Publication date
JPS5938671B2 (en) 1984-09-18

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