JPS5468134A - Interruption system - Google Patents

Interruption system

Info

Publication number
JPS5468134A
JPS5468134A JP13479477A JP13479477A JPS5468134A JP S5468134 A JPS5468134 A JP S5468134A JP 13479477 A JP13479477 A JP 13479477A JP 13479477 A JP13479477 A JP 13479477A JP S5468134 A JPS5468134 A JP S5468134A
Authority
JP
Japan
Prior art keywords
interruption
status
register
output
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13479477A
Other languages
Japanese (ja)
Inventor
Shigeo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13479477A priority Critical patent/JPS5468134A/en
Publication of JPS5468134A publication Critical patent/JPS5468134A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the working rate of the main body, by simplifying the series control program of the input unit, through the processing causing interruption if the state designated by the program is taken place.
CONSTITUTION: The interruption system is constituted by providing CPU 1, register 2 holding the data selecting one status from the status group 4, and the control section 3 controlling the output of the interruption line 5 with the output of the status selected with the data of the register 2. Further, the data selecting the status designated with CPU 1 is loaded to the register 2 and when the output of the status line designated, with the data of the register 2 is the output designated, interruption signal is fed to the interruption line 5 from the control section 3 and interruption processing is executed with CPU 1 by means of the interruption signal.
COPYRIGHT: (C)1979,JPO&Japio
JP13479477A 1977-11-11 1977-11-11 Interruption system Pending JPS5468134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13479477A JPS5468134A (en) 1977-11-11 1977-11-11 Interruption system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13479477A JPS5468134A (en) 1977-11-11 1977-11-11 Interruption system

Publications (1)

Publication Number Publication Date
JPS5468134A true JPS5468134A (en) 1979-06-01

Family

ID=15136685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13479477A Pending JPS5468134A (en) 1977-11-11 1977-11-11 Interruption system

Country Status (1)

Country Link
JP (1) JPS5468134A (en)

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