JPS5469938A - Indirect-address modifying unit - Google Patents

Indirect-address modifying unit

Info

Publication number
JPS5469938A
JPS5469938A JP13696877A JP13696877A JPS5469938A JP S5469938 A JPS5469938 A JP S5469938A JP 13696877 A JP13696877 A JP 13696877A JP 13696877 A JP13696877 A JP 13696877A JP S5469938 A JPS5469938 A JP S5469938A
Authority
JP
Japan
Prior art keywords
register
address
instruction
indirect
modification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13696877A
Other languages
Japanese (ja)
Inventor
Michio Arai
Yasuo Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13696877A priority Critical patent/JPS5469938A/en
Publication of JPS5469938A publication Critical patent/JPS5469938A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To lighten a burden upon software by providing hardware for address modification.
CONSTITUTION: When read out to instruction register 11, specific instruction (EXa) for indirect address modification assignment is stored in internal holding register 12, and EXa-assigning FF13 is set. Next, when load instruction is read out to register 11, operand calculation is executed according to this load instruction, but since set at this time, gate control signal GC for address modification is outputted from modification control circuit 16 and by this signal, the results of the operand calculation obtained from arithmetic circuit 19 are loaded to memory address register 20. After read-out contents of memory unit 21 assigned in accordance with the contents of register 20 are stored in memory data register 22, they are loaded again to register 20 by way of selection gate 23.
COPYRIGHT: (C)1979,JPO&Japio
JP13696877A 1977-11-15 1977-11-15 Indirect-address modifying unit Pending JPS5469938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13696877A JPS5469938A (en) 1977-11-15 1977-11-15 Indirect-address modifying unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13696877A JPS5469938A (en) 1977-11-15 1977-11-15 Indirect-address modifying unit

Publications (1)

Publication Number Publication Date
JPS5469938A true JPS5469938A (en) 1979-06-05

Family

ID=15187680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13696877A Pending JPS5469938A (en) 1977-11-15 1977-11-15 Indirect-address modifying unit

Country Status (1)

Country Link
JP (1) JPS5469938A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934747A (en) * 1972-08-01 1974-03-30

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934747A (en) * 1972-08-01 1974-03-30

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