JPS5474629A - Display system for dot pattern - Google Patents

Display system for dot pattern

Info

Publication number
JPS5474629A
JPS5474629A JP14158577A JP14158577A JPS5474629A JP S5474629 A JPS5474629 A JP S5474629A JP 14158577 A JP14158577 A JP 14158577A JP 14158577 A JP14158577 A JP 14158577A JP S5474629 A JPS5474629 A JP S5474629A
Authority
JP
Japan
Prior art keywords
dot pattern
ram
generator
address
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14158577A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14158577A priority Critical patent/JPS5474629A/en
Publication of JPS5474629A publication Critical patent/JPS5474629A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: To enable to form letters, and graphs freely, by changing the character generator forming dot pattern with program and forming arbitrary pattern of free code with software.
CONSTITUTION: The character generator 1 forming dot pattern is provided with so- called RAM 2, constituting the system outputting the dot pattern formed by taking the RAM inputs A and RAM address B as the RAM output C. Further, the address B is given to the RAM 2 and the data A is given to the generator 1, writing in instructions to the generator 1. After that, the address B is given and the dot pattern is formed, outputting the RAM output C. With this constitution, the dot pattern displayed with the program changed for giving to the generator 1 is displayed after being altered to arbitrary pattern.
COPYRIGHT: (C)1979,JPO&Japio
JP14158577A 1977-11-28 1977-11-28 Display system for dot pattern Pending JPS5474629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14158577A JPS5474629A (en) 1977-11-28 1977-11-28 Display system for dot pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14158577A JPS5474629A (en) 1977-11-28 1977-11-28 Display system for dot pattern

Publications (1)

Publication Number Publication Date
JPS5474629A true JPS5474629A (en) 1979-06-14

Family

ID=15295415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14158577A Pending JPS5474629A (en) 1977-11-28 1977-11-28 Display system for dot pattern

Country Status (1)

Country Link
JP (1) JPS5474629A (en)

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