JPS5475242A - Interrupt processing system - Google Patents

Interrupt processing system

Info

Publication number
JPS5475242A
JPS5475242A JP14291177A JP14291177A JPS5475242A JP S5475242 A JPS5475242 A JP S5475242A JP 14291177 A JP14291177 A JP 14291177A JP 14291177 A JP14291177 A JP 14291177A JP S5475242 A JPS5475242 A JP S5475242A
Authority
JP
Japan
Prior art keywords
interrupt
processor
memory
processing routine
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14291177A
Other languages
Japanese (ja)
Inventor
Akira Tokunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14291177A priority Critical patent/JPS5475242A/en
Publication of JPS5475242A publication Critical patent/JPS5475242A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To omit steps for check to perform an interrupt processing dependent upon high-speed firmware by constituting this system so that the jumping to a corresponding processing routine may be performed without checking interrupt causes and internal state.
CONSTITUTION: In the information processing unit consisting of processor 3 and I/O devices which are connected to bus 1, control memory 2 to store the firmware which regulates the operation of processor 3 is provided, and processor 3 executes arithmetic operations and processings dependently upon the firmware stored in memory 2. Further, interrupt control circuit 4 to control interrupts on a basis of the instruction of processor 3, memory 5 to store the processing routine corresponding to an interrupt cause, and register group 6 to store the address of the interrupt processing routine are provided. Then, processor 3 sets contents of register 2 on a basis of the internal state of the processing unit; and when the interrupt request from the external has come, the jumping to the corresponding processing routine in memory 5 is performed on a basis of contents of register 2.
COPYRIGHT: (C)1979,JPO&Japio
JP14291177A 1977-11-29 1977-11-29 Interrupt processing system Pending JPS5475242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14291177A JPS5475242A (en) 1977-11-29 1977-11-29 Interrupt processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14291177A JPS5475242A (en) 1977-11-29 1977-11-29 Interrupt processing system

Publications (1)

Publication Number Publication Date
JPS5475242A true JPS5475242A (en) 1979-06-15

Family

ID=15326474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14291177A Pending JPS5475242A (en) 1977-11-29 1977-11-29 Interrupt processing system

Country Status (1)

Country Link
JP (1) JPS5475242A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212550A (en) * 1981-06-24 1982-12-27 Fujitsu Ltd Extension system for software interruption level

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212550A (en) * 1981-06-24 1982-12-27 Fujitsu Ltd Extension system for software interruption level

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