JPS5477033A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5477033A
JPS5477033A JP14393477A JP14393477A JPS5477033A JP S5477033 A JPS5477033 A JP S5477033A JP 14393477 A JP14393477 A JP 14393477A JP 14393477 A JP14393477 A JP 14393477A JP S5477033 A JPS5477033 A JP S5477033A
Authority
JP
Japan
Prior art keywords
write
control circuit
signal
read
starting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14393477A
Other languages
Japanese (ja)
Inventor
Yusuke Kamitsuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14393477A priority Critical patent/JPS5477033A/en
Publication of JPS5477033A publication Critical patent/JPS5477033A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To shorten a write time by starting a write operation right after a write signal arrives with no write-signal acceptance time by equipping a memory unit, used by various equipments in common, with a timing control circuit exclusively used for the write operation. CONSTITUTION:Once receiving starting signal 10, read-operation control circuit 5 generates timing used for both read operation and write operation. Receiving a write signal within the write-signal acceptance time, write-operation control circuit 6 inhibits immediately read-operation control circuit 5 from starting its read operation. Write information is fetched in formation control circuit 4 and then sent to memory part 3. Next, the timing needed for writing is sent to memory part 3 via driver circuit 2 and the write operation is finished within a fixed time by the write signal.
JP14393477A 1977-12-02 1977-12-02 Memory unit Pending JPS5477033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14393477A JPS5477033A (en) 1977-12-02 1977-12-02 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14393477A JPS5477033A (en) 1977-12-02 1977-12-02 Memory unit

Publications (1)

Publication Number Publication Date
JPS5477033A true JPS5477033A (en) 1979-06-20

Family

ID=15350463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14393477A Pending JPS5477033A (en) 1977-12-02 1977-12-02 Memory unit

Country Status (1)

Country Link
JP (1) JPS5477033A (en)

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