JPS5477879A - Sequence control method - Google Patents

Sequence control method

Info

Publication number
JPS5477879A
JPS5477879A JP14451877A JP14451877A JPS5477879A JP S5477879 A JPS5477879 A JP S5477879A JP 14451877 A JP14451877 A JP 14451877A JP 14451877 A JP14451877 A JP 14451877A JP S5477879 A JPS5477879 A JP S5477879A
Authority
JP
Japan
Prior art keywords
code
condition
addrress
awc
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14451877A
Other languages
Japanese (ja)
Inventor
Tadahiro Yanagisawa
Matsuo Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14451877A priority Critical patent/JPS5477879A/en
Publication of JPS5477879A publication Critical patent/JPS5477879A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE: A sequence controlling method of a stored program intended the shortening of the operation requiring time, by means of subjecting to be jumped over the addrress appointment of a memory according as the completeness or the uncompleteness of the appointed condition.
CONSTITUTION: In a case when a sequence control circuit such as so connecting as that always opened contacts A, B, C and E are connected in parallel to a relay X, and an always opened contact D is connected in series to the contacts AWC, is controlled as a logic block drawing shown in the right, the memory memorizes a multiple signal of the logic AND, a jump code 4, condition codes AWC, an addition code of the logic OR, a condition code D, a multiple code AND, a condition code E, an output code OUT, and a control object code X according to the order of the adrress, and the content of a jump code is specified as that when the appointed condition is uncompleted by the following condition codes AWC, a jumping is effected from the addrress of this code 4 to the addrress of the fourth addrress.
COPYRIGHT: (C)1979,JPO&Japio
JP14451877A 1977-12-01 1977-12-01 Sequence control method Pending JPS5477879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14451877A JPS5477879A (en) 1977-12-01 1977-12-01 Sequence control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14451877A JPS5477879A (en) 1977-12-01 1977-12-01 Sequence control method

Publications (1)

Publication Number Publication Date
JPS5477879A true JPS5477879A (en) 1979-06-21

Family

ID=15364197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14451877A Pending JPS5477879A (en) 1977-12-01 1977-12-01 Sequence control method

Country Status (1)

Country Link
JP (1) JPS5477879A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57134707A (en) * 1981-02-12 1982-08-20 Hitachi Seiko Ltd Relay type sequence controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57134707A (en) * 1981-02-12 1982-08-20 Hitachi Seiko Ltd Relay type sequence controller

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