JPS5480045A - Pure binary number input decimal number conversion device - Google Patents

Pure binary number input decimal number conversion device

Info

Publication number
JPS5480045A
JPS5480045A JP14711677A JP14711677A JPS5480045A JP S5480045 A JPS5480045 A JP S5480045A JP 14711677 A JP14711677 A JP 14711677A JP 14711677 A JP14711677 A JP 14711677A JP S5480045 A JPS5480045 A JP S5480045A
Authority
JP
Japan
Prior art keywords
residual
binary number
pure binary
conversion
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14711677A
Other languages
Japanese (ja)
Inventor
Tadashi Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14711677A priority Critical patent/JPS5480045A/en
Publication of JPS5480045A publication Critical patent/JPS5480045A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To ensure the simultaneous performance of the code conversion and the serial conversion through one unit of the circuit by securing the output of 1/10 + residual pure binary number to the input of the pure binary number for the contents of the code converter and repeating this conversion in time division to deliver the residual in sequence via the memory element.
CONSTITUTION: Pure binary number input 6 is applied to data switch 1, and input 6 is set to temporary memory element 2 via switch signal 9 and writing stignal 10. This set value is calculated at ROM3 to deliver 1/10 pure binary number 7 plus residual 8. Residual 8 is then displayed to prescribed indicator 5 via displaY signals 11W13. The calculated number 7 is fed back to switch 1 to carry out the operation of 1/100, and the same action as the preceding action is repeated to display residual 8 to indicator 5. This conversion is repeated in time division to perform both the code conversion and the serial conversion at one time.
COPYRIGHT: (C)1979,JPO&Japio
JP14711677A 1977-12-09 1977-12-09 Pure binary number input decimal number conversion device Pending JPS5480045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14711677A JPS5480045A (en) 1977-12-09 1977-12-09 Pure binary number input decimal number conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14711677A JPS5480045A (en) 1977-12-09 1977-12-09 Pure binary number input decimal number conversion device

Publications (1)

Publication Number Publication Date
JPS5480045A true JPS5480045A (en) 1979-06-26

Family

ID=15422881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14711677A Pending JPS5480045A (en) 1977-12-09 1977-12-09 Pure binary number input decimal number conversion device

Country Status (1)

Country Link
JP (1) JPS5480045A (en)

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