JPS5480049A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5480049A
JPS5480049A JP14706977A JP14706977A JPS5480049A JP S5480049 A JPS5480049 A JP S5480049A JP 14706977 A JP14706977 A JP 14706977A JP 14706977 A JP14706977 A JP 14706977A JP S5480049 A JPS5480049 A JP S5480049A
Authority
JP
Japan
Prior art keywords
microorder
jump
address
register
data register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14706977A
Other languages
Japanese (ja)
Inventor
Tokumitsu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14706977A priority Critical patent/JPS5480049A/en
Publication of JPS5480049A publication Critical patent/JPS5480049A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the bit width of the ROM as well as to maximize the process speed by supplying the output of the 1st data register to the address controller via the control signal output of the 2nd data register to fetch the microorder of the jump address.
CONSTITUTION: The jump command containing the condition data and the jump address as the paramenter arrives from outside to fetch the control information of the next order and the further subsequent microorder while the arithmetic process is being executed for a certain microorder. Then the control signal of the jump command is ratched to 2nd data register 16, and at the same time the jump address is ratched to 1st data register 13. After this, the output of register 13 is supplied to address controller 11 via the control signal output of register 16 to fetch the microorder of the jump address.
COPYRIGHT: (C)1979,JPO&Japio
JP14706977A 1977-12-09 1977-12-09 Microprogram control system Pending JPS5480049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14706977A JPS5480049A (en) 1977-12-09 1977-12-09 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14706977A JPS5480049A (en) 1977-12-09 1977-12-09 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5480049A true JPS5480049A (en) 1979-06-26

Family

ID=15421767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14706977A Pending JPS5480049A (en) 1977-12-09 1977-12-09 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5480049A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785147A (en) * 1980-11-18 1982-05-27 Fujitsu Ltd Microprogram control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785147A (en) * 1980-11-18 1982-05-27 Fujitsu Ltd Microprogram control device

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