JPS5480631A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5480631A
JPS5480631A JP14787977A JP14787977A JPS5480631A JP S5480631 A JPS5480631 A JP S5480631A JP 14787977 A JP14787977 A JP 14787977A JP 14787977 A JP14787977 A JP 14787977A JP S5480631 A JPS5480631 A JP S5480631A
Authority
JP
Japan
Prior art keywords
memory
slave
condition
address
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14787977A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14787977A priority Critical patent/JPS5480631A/en
Publication of JPS5480631A publication Critical patent/JPS5480631A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To reduce the restriction on program formation, by reducing the processing time and number of steps of program, through enabling to select the main memory and slave memory without exection of instruction. CONSTITUTION:When two memory sections 2 and 3 are selected, the limitation that only when the address satisfies a condition, the slave memory can be selected, without the operation of selection only with FF4. Thus, even if the selection FF is set, when the address not satisfies the condition, the main memory is selected and if satisfied, the slave memory is selected. That is, the master and slave can be selected with FF set. The memory capacity for the slave memory is limited with the addition of the address condition, but since the slave memory has smaller capacity than the main memory in general, it is not unnatural. With this consitution, the master and slave memory can freely be selected without the selection instruction, allowing to reduce the number of steps and processing time.
JP14787977A 1977-12-09 1977-12-09 Memory unit Pending JPS5480631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14787977A JPS5480631A (en) 1977-12-09 1977-12-09 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14787977A JPS5480631A (en) 1977-12-09 1977-12-09 Memory unit

Publications (1)

Publication Number Publication Date
JPS5480631A true JPS5480631A (en) 1979-06-27

Family

ID=15440279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14787977A Pending JPS5480631A (en) 1977-12-09 1977-12-09 Memory unit

Country Status (1)

Country Link
JP (1) JPS5480631A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112547A (en) * 1973-02-06 1974-10-26
JPS49113540A (en) * 1973-02-26 1974-10-30
JPS513538A (en) * 1974-06-27 1976-01-13 Tokyo Shibaura Electric Co
JPS5171648A (en) * 1974-12-18 1976-06-21 Panafacom Ltd

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112547A (en) * 1973-02-06 1974-10-26
JPS49113540A (en) * 1973-02-26 1974-10-30
JPS513538A (en) * 1974-06-27 1976-01-13 Tokyo Shibaura Electric Co
JPS5171648A (en) * 1974-12-18 1976-06-21 Panafacom Ltd

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