JPS5480660A - Frequency demultiplication circuit - Google Patents
Frequency demultiplication circuitInfo
- Publication number
- JPS5480660A JPS5480660A JP14774177A JP14774177A JPS5480660A JP S5480660 A JPS5480660 A JP S5480660A JP 14774177 A JP14774177 A JP 14774177A JP 14774177 A JP14774177 A JP 14774177A JP S5480660 A JPS5480660 A JP S5480660A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- counter
- preset
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000977 initiatory effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
Landscapes
- Manipulation Of Pulses (AREA)
- Electric Clocks (AREA)
Abstract
PURPOSE:To establish the frequency demultiplication circuit which is enabled to be small chips even with the CMOS integrated circuit having high speed operation used. CONSTITUTION:The frequency demultiplication system uses the expandor preset system, and when ''202'' is preset and the counters at post stage are all at ''0'', the output of the carrier out circuit 14 is ''1'', the output of the first memory circuit 14 is also ''1'' and ''200'' is preset with the output ''1'' of the first memory circui 15 with the post stage counter. Thus, the output of the counter of ''200'' is ''1'' and the output of the circuit 14 is ''0''. Assuming that all the flip flop circuits are operated at leading, the output of the first memory circuit 15 memorizes ''1''. Succeedingly, the counter 1 of the first stage is ''1'' with the input clock signals (8 signals) fed, and the output of the first stage carry out circuit 16 is ''1''. As a result, the output of the memory circuit 17 is also ''1'', ''2'' is preset for the counter 1 and the circuit 15 is reset, the output of the circuit 16 is ''0'', initiating normal count down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14774177A JPS5480660A (en) | 1977-12-10 | 1977-12-10 | Frequency demultiplication circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14774177A JPS5480660A (en) | 1977-12-10 | 1977-12-10 | Frequency demultiplication circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5480660A true JPS5480660A (en) | 1979-06-27 |
| JPS6123896B2 JPS6123896B2 (en) | 1986-06-07 |
Family
ID=15437085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14774177A Granted JPS5480660A (en) | 1977-12-10 | 1977-12-10 | Frequency demultiplication circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5480660A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5726931A (en) * | 1980-07-24 | 1982-02-13 | Nec Corp | Programmable counter |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4287430A4 (en) * | 2021-01-27 | 2024-11-06 | Sansha Electric Manufacturing Co., Ltd. | POWER SUPPLY SYSTEM AND POWER SUPPLY UNIT |
-
1977
- 1977-12-10 JP JP14774177A patent/JPS5480660A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5726931A (en) * | 1980-07-24 | 1982-02-13 | Nec Corp | Programmable counter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6123896B2 (en) | 1986-06-07 |
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