JPS5485663A - Electronic timer - Google Patents

Electronic timer

Info

Publication number
JPS5485663A
JPS5485663A JP15400077A JP15400077A JPS5485663A JP S5485663 A JPS5485663 A JP S5485663A JP 15400077 A JP15400077 A JP 15400077A JP 15400077 A JP15400077 A JP 15400077A JP S5485663 A JPS5485663 A JP S5485663A
Authority
JP
Japan
Prior art keywords
circuit
gate
switches
time
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15400077A
Other languages
Japanese (ja)
Inventor
Yoshio Nakada
Saichi Amakawa
Mikio Akita
Shiro Senaka
Yoshiaki Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15400077A priority Critical patent/JPS5485663A/en
Publication of JPS5485663A publication Critical patent/JPS5485663A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Landscapes

  • Measurement Of Predetermined Time Intervals (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain the timer simple in the circuit and with good operationability, by judging the logic condition for the primary and secondary of the time set switch and resetting the output signal hold circuit only when the set switch is changed over. CONSTITUTION:The counter 1 demultiplies the commercial frequency, and the output is held with the OR gates 02 to 04 and inverter I1 through the time set switches S1 to S8 and the NAND gates N1 to N8 of the output signal circuit 2. The reset circuit 4 resets the circuit 3, when all the signals from the NAND gates N9 and N10 and OR gate 01 connected to the primary gates N1 to N8 of the switches S1 to S8 and that from the OR gate 04 of the switch secondary are low, that is, when no time set is made or at momentary time of set switch changeover, with the output of NOR gate RG1 in high state. Further, when either of the switches is closed, or after the set time reaches, the two inputs of RG1 are low and high and no circuit 3 is reset.
JP15400077A 1977-12-20 1977-12-20 Electronic timer Pending JPS5485663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15400077A JPS5485663A (en) 1977-12-20 1977-12-20 Electronic timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15400077A JPS5485663A (en) 1977-12-20 1977-12-20 Electronic timer

Publications (1)

Publication Number Publication Date
JPS5485663A true JPS5485663A (en) 1979-07-07

Family

ID=15574715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15400077A Pending JPS5485663A (en) 1977-12-20 1977-12-20 Electronic timer

Country Status (1)

Country Link
JP (1) JPS5485663A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197088U (en) * 1981-06-09 1982-12-14
JPS61143337U (en) * 1985-02-26 1986-09-04

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197088U (en) * 1981-06-09 1982-12-14
JPS61143337U (en) * 1985-02-26 1986-09-04

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