JPS5487029A - Information transfer system - Google Patents

Information transfer system

Info

Publication number
JPS5487029A
JPS5487029A JP15483577A JP15483577A JPS5487029A JP S5487029 A JPS5487029 A JP S5487029A JP 15483577 A JP15483577 A JP 15483577A JP 15483577 A JP15483577 A JP 15483577A JP S5487029 A JPS5487029 A JP S5487029A
Authority
JP
Japan
Prior art keywords
circuit
data
register
information transfer
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15483577A
Other languages
Japanese (ja)
Inventor
Nobuharu Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15483577A priority Critical patent/JPS5487029A/en
Publication of JPS5487029A publication Critical patent/JPS5487029A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE: To ensure the information transfer with use of other non-defective information transfer line in case some defect is detected at part of an information transfer line.
CONSTITUTION: At the normal operation time, the data of data register AO is transferred to data register EO through data line 4-0, and at the same time the data of data register A1 is transferred to data register E1 through data line 4-1. In case some error is detected at line 4-0, register F0 and G0 are set. And AND circuit a0 and a1 are opened, and b0 is closed with AND circuit d0 circuit d0 and d1 opened. In this case, the data within A0 is transferred to register E0 via register B0→a1÷OR circuit 16-1→AND circuit b1→data line 4-1→circuit d1→OR circuit 18-0→AND circuit E0 respectively. The data within A1 is transferred to register E1 via circuit 16-1→circuit b1→data line 4-1→circuit d1→register D1→OR circuit 18-1-AND circuit e1 respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP15483577A 1977-12-22 1977-12-22 Information transfer system Pending JPS5487029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15483577A JPS5487029A (en) 1977-12-22 1977-12-22 Information transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15483577A JPS5487029A (en) 1977-12-22 1977-12-22 Information transfer system

Publications (1)

Publication Number Publication Date
JPS5487029A true JPS5487029A (en) 1979-07-11

Family

ID=15592914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15483577A Pending JPS5487029A (en) 1977-12-22 1977-12-22 Information transfer system

Country Status (1)

Country Link
JP (1) JPS5487029A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5876924A (en) * 1981-10-30 1983-05-10 Nec Corp Data transfer device
JPS62114054A (en) * 1985-11-13 1987-05-25 Yokogawa Electric Corp Data transfer device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5876924A (en) * 1981-10-30 1983-05-10 Nec Corp Data transfer device
JPS62114054A (en) * 1985-11-13 1987-05-25 Yokogawa Electric Corp Data transfer device

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