JPS5489437A - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- JPS5489437A JPS5489437A JP15832077A JP15832077A JPS5489437A JP S5489437 A JPS5489437 A JP S5489437A JP 15832077 A JP15832077 A JP 15832077A JP 15832077 A JP15832077 A JP 15832077A JP S5489437 A JPS5489437 A JP S5489437A
- Authority
- JP
- Japan
- Prior art keywords
- information
- buffer memory
- substitutional
- block
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To determine the priority order of substitutional blocks in a simple configuration by providing a control bit in the substitutional block and indicating the priority of information to be left in the buffer memory at a memory information substitution time in the buffer memory.
CONSTITUTION: By instruction request signal IS, update circuit NC updates substitutional information in substitutional information memory part CM through FF. Substitutional information consists of control bit A corresponding to the number of blocks in the buffer memory and order information B, and control bit A corresponding to the block according to signal IS is written in memory part CM. Store block determination circuit SB determines a block in the buffer memory where information read from the main memory is to be stored, and outputs store block address SBA. In case of the block substitution in the buffer memory, substitution is performed according to order information B except blocks where control bit A is "1", and instructions which are used repeatedly with a high frequency are left in the buffer memory.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15832077A JPS5489437A (en) | 1977-12-27 | 1977-12-27 | Buffer memory control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15832077A JPS5489437A (en) | 1977-12-27 | 1977-12-27 | Buffer memory control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5489437A true JPS5489437A (en) | 1979-07-16 |
Family
ID=15669050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15832077A Pending JPS5489437A (en) | 1977-12-27 | 1977-12-27 | Buffer memory control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5489437A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62156744A (en) * | 1985-12-23 | 1987-07-11 | モトロ−ラ・インコ−ポレ−テツド | Cash memory |
| JPH07182235A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Information processor |
-
1977
- 1977-12-27 JP JP15832077A patent/JPS5489437A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62156744A (en) * | 1985-12-23 | 1987-07-11 | モトロ−ラ・インコ−ポレ−テツド | Cash memory |
| JPH07182235A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Information processor |
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