JPS5489437A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5489437A
JPS5489437A JP15832077A JP15832077A JPS5489437A JP S5489437 A JPS5489437 A JP S5489437A JP 15832077 A JP15832077 A JP 15832077A JP 15832077 A JP15832077 A JP 15832077A JP S5489437 A JPS5489437 A JP S5489437A
Authority
JP
Japan
Prior art keywords
information
buffer memory
substitutional
block
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15832077A
Other languages
Japanese (ja)
Inventor
Satoshi Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15832077A priority Critical patent/JPS5489437A/en
Publication of JPS5489437A publication Critical patent/JPS5489437A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To determine the priority order of substitutional blocks in a simple configuration by providing a control bit in the substitutional block and indicating the priority of information to be left in the buffer memory at a memory information substitution time in the buffer memory.
CONSTITUTION: By instruction request signal IS, update circuit NC updates substitutional information in substitutional information memory part CM through FF. Substitutional information consists of control bit A corresponding to the number of blocks in the buffer memory and order information B, and control bit A corresponding to the block according to signal IS is written in memory part CM. Store block determination circuit SB determines a block in the buffer memory where information read from the main memory is to be stored, and outputs store block address SBA. In case of the block substitution in the buffer memory, substitution is performed according to order information B except blocks where control bit A is "1", and instructions which are used repeatedly with a high frequency are left in the buffer memory.
COPYRIGHT: (C)1979,JPO&Japio
JP15832077A 1977-12-27 1977-12-27 Buffer memory control system Pending JPS5489437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15832077A JPS5489437A (en) 1977-12-27 1977-12-27 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15832077A JPS5489437A (en) 1977-12-27 1977-12-27 Buffer memory control system

Publications (1)

Publication Number Publication Date
JPS5489437A true JPS5489437A (en) 1979-07-16

Family

ID=15669050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15832077A Pending JPS5489437A (en) 1977-12-27 1977-12-27 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS5489437A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156744A (en) * 1985-12-23 1987-07-11 モトロ−ラ・インコ−ポレ−テツド Cash memory
JPH07182235A (en) * 1993-12-24 1995-07-21 Nec Corp Information processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156744A (en) * 1985-12-23 1987-07-11 モトロ−ラ・インコ−ポレ−テツド Cash memory
JPH07182235A (en) * 1993-12-24 1995-07-21 Nec Corp Information processor

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