JPS5491064A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5491064A
JPS5491064A JP15874077A JP15874077A JPS5491064A JP S5491064 A JPS5491064 A JP S5491064A JP 15874077 A JP15874077 A JP 15874077A JP 15874077 A JP15874077 A JP 15874077A JP S5491064 A JPS5491064 A JP S5491064A
Authority
JP
Japan
Prior art keywords
layer
emitter
base
layers
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15874077A
Other languages
Japanese (ja)
Inventor
Hajime Kamioka
Mikio Takagi
Hiroo Sasaki
Akira Fujinuma
Yoshio Akai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15874077A priority Critical patent/JPS5491064A/en
Publication of JPS5491064A publication Critical patent/JPS5491064A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To improve emitter-base dielectric strength at the time of the manufacture of a high-speed bipolar transistor, and to prevent an alloyed layer from penetrating an emitter layer during the formation of an ohmic electrode.
CONSTITUTION: In thin film 20 of oxidized film 6 on P-type Si substrate 1 with N+-type buried layer 2, an opening is made by a Si3N4 21 mask. Both P-type base connection layers 22 and 23 are formed and then covered with SiO2 layers 24 and 25. Next, films 20 and 21 are removed and B is diffused again to form shallow base layer 26. After coating with poly-Si 27, phosphorus ions are injected to form emitter layer 28 and ions are activated through a treatment at 950°C for ten minutes in N2. At this time, layer 27 becomes conductive. Lastly, layer 27 is patterned and the emitter electeode part is made to remain before a window is provided into films 24 and 25. Then, Al electrode is selectively formed and layer 27 and layers 22 and 23 are made in ohmic contact. Consequently, the base layer will not become thinner, base-emitter dielectric strength improves and Al will not penetrate the emitter layer.
COPYRIGHT: (C)1979,JPO&Japio
JP15874077A 1977-12-28 1977-12-28 Manufacture of semiconductor device Pending JPS5491064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15874077A JPS5491064A (en) 1977-12-28 1977-12-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15874077A JPS5491064A (en) 1977-12-28 1977-12-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5491064A true JPS5491064A (en) 1979-07-19

Family

ID=15678289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15874077A Pending JPS5491064A (en) 1977-12-28 1977-12-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5491064A (en)

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