JPS5493320A - Delivery system of narrow band picture - Google Patents

Delivery system of narrow band picture

Info

Publication number
JPS5493320A
JPS5493320A JP15841577A JP15841577A JPS5493320A JP S5493320 A JPS5493320 A JP S5493320A JP 15841577 A JP15841577 A JP 15841577A JP 15841577 A JP15841577 A JP 15841577A JP S5493320 A JPS5493320 A JP S5493320A
Authority
JP
Japan
Prior art keywords
memory
circuit
signal
data
converted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15841577A
Other languages
Japanese (ja)
Inventor
Toru Yagihashi
Shigeru Suzuki
Masakatsu Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15841577A priority Critical patent/JPS5493320A/en
Publication of JPS5493320A publication Critical patent/JPS5493320A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to shorten the picture producing time, by producing the digital video signal with the video transmitter in arbitrary rate of dot interlace and line interlace.
CONSTITUTION: The video signal from the television camera 1 is D/A converted 2 and stored in the one picture memory 3. The transmission circuit 4 feeds the signal from the memory 3 to the MODEM 5 and delivers it to the line after being converted into the delivery signal in the MODEM5. The control circuit 6 controls the address conversion circuit 7 depending on the dot line interlace to be executed, determining the address of data delivered with the circuit 7, and the data from the memory 3 is delivered to the circuit 4. At the reception side, the signal converted into the data of picture with the MODEM11 and the reception circuit 12 is memorized in the one screen memory 13. The address conversion circuit 14 repetitively reproduces the transmission data immediately before at the period when no data is fed from the transmission side for the interlace with the control circuit 15 and stores it in the memory 13. The signal from the memory 13 is D/A converted 16 and reproduced with the receiver 17.
COPYRIGHT: (C)1979,JPO&Japio
JP15841577A 1977-12-30 1977-12-30 Delivery system of narrow band picture Pending JPS5493320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15841577A JPS5493320A (en) 1977-12-30 1977-12-30 Delivery system of narrow band picture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15841577A JPS5493320A (en) 1977-12-30 1977-12-30 Delivery system of narrow band picture

Publications (1)

Publication Number Publication Date
JPS5493320A true JPS5493320A (en) 1979-07-24

Family

ID=15671248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15841577A Pending JPS5493320A (en) 1977-12-30 1977-12-30 Delivery system of narrow band picture

Country Status (1)

Country Link
JP (1) JPS5493320A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5684086A (en) * 1979-12-12 1981-07-09 Mitsubishi Electric Corp Still picture transmitter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5684086A (en) * 1979-12-12 1981-07-09 Mitsubishi Electric Corp Still picture transmitter

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