JPS5496334A - Digital signal bus - Google Patents

Digital signal bus

Info

Publication number
JPS5496334A
JPS5496334A JP281178A JP281178A JPS5496334A JP S5496334 A JPS5496334 A JP S5496334A JP 281178 A JP281178 A JP 281178A JP 281178 A JP281178 A JP 281178A JP S5496334 A JPS5496334 A JP S5496334A
Authority
JP
Japan
Prior art keywords
bus
caused
wiring
noise
differential transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP281178A
Other languages
Japanese (ja)
Inventor
Shoji Matoba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP281178A priority Critical patent/JPS5496334A/en
Publication of JPS5496334A publication Critical patent/JPS5496334A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To decrease the number of the wiring as well as the number of the pin in each package by securing the positional isolation for the wirings between different buses and giving the differential transmission only for the gate signal.
CONSTITUTION: The bus comprises unbalanced transmission DA1WDAm and DB1W DBn caused by the single wiring plus differential transmission GA and GB caused by the approximating parallel wirings or the twisted paired wires, and 1st bus A is isolated from 2nd bus B in terms of their positions. The induction noise is erased to GA and GB through the differential transmission, and the phase of noise N induced to DA1WDAm and DB1WDBn is fixed by isolation between buses. Thus, the noise caused from the data and address signal can be deleted by the gate signal at the reception circuit. Furthermore, the number of the wiring and the pin can be reduced by m + n pieces.
COPYRIGHT: (C)1979,JPO&Japio
JP281178A 1978-01-17 1978-01-17 Digital signal bus Pending JPS5496334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP281178A JPS5496334A (en) 1978-01-17 1978-01-17 Digital signal bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP281178A JPS5496334A (en) 1978-01-17 1978-01-17 Digital signal bus

Publications (1)

Publication Number Publication Date
JPS5496334A true JPS5496334A (en) 1979-07-30

Family

ID=11539767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP281178A Pending JPS5496334A (en) 1978-01-17 1978-01-17 Digital signal bus

Country Status (1)

Country Link
JP (1) JPS5496334A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04149682A (en) * 1990-10-09 1992-05-22 Mitsubishi Electric Corp Noise prevention circuit for microcomputer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504085A (en) * 1972-01-15 1975-01-16
JPS5247339A (en) * 1975-10-13 1977-04-15 Nec Corp Signal bus bar transmission system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504085A (en) * 1972-01-15 1975-01-16
JPS5247339A (en) * 1975-10-13 1977-04-15 Nec Corp Signal bus bar transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04149682A (en) * 1990-10-09 1992-05-22 Mitsubishi Electric Corp Noise prevention circuit for microcomputer

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