JPS5496384A - Method of and structure for crossing information signal for ic - Google Patents

Method of and structure for crossing information signal for ic

Info

Publication number
JPS5496384A
JPS5496384A JP8760878A JP8760878A JPS5496384A JP S5496384 A JPS5496384 A JP S5496384A JP 8760878 A JP8760878 A JP 8760878A JP 8760878 A JP8760878 A JP 8760878A JP S5496384 A JPS5496384 A JP S5496384A
Authority
JP
Japan
Prior art keywords
information signal
crossing information
crossing
signal
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8760878A
Other languages
English (en)
Japanese (ja)
Inventor
Uooresu Doochieru Harorudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of JPS5496384A publication Critical patent/JPS5496384A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Waveguides (AREA)
JP8760878A 1977-07-18 1978-07-18 Method of and structure for crossing information signal for ic Pending JPS5496384A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81636577A 1977-07-18 1977-07-18

Publications (1)

Publication Number Publication Date
JPS5496384A true JPS5496384A (en) 1979-07-30

Family

ID=25220405

Family Applications (2)

Application Number Title Priority Date Filing Date
JP8760878A Pending JPS5496384A (en) 1977-07-18 1978-07-18 Method of and structure for crossing information signal for ic
JP1983183901U Pending JPS59112944U (ja) 1977-07-18 1983-11-30 集積回路

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP1983183901U Pending JPS59112944U (ja) 1977-07-18 1983-11-30 集積回路

Country Status (5)

Country Link
JP (2) JPS5496384A (it)
DE (1) DE2831523A1 (it)
FR (1) FR2398386A1 (it)
GB (1) GB2001472B (it)
IT (1) IT1097967B (it)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550652A (en) * 1978-09-19 1980-04-12 Agency Of Ind Science & Technol Composite element adjusting method by ion beam

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381595A (en) * 1979-10-09 1983-05-03 Mitsubishi Denki Kabushiki Kaisha Process for preparing multilayer interconnection

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921282A (en) * 1971-02-16 1975-11-25 Texas Instruments Inc Insulated gate field effect transistor circuits and their method of fabrication
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
JPS5947464B2 (ja) * 1974-09-11 1984-11-19 株式会社日立製作所 半導体装置
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
US4035198A (en) * 1976-06-30 1977-07-12 International Business Machines Corporation Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550652A (en) * 1978-09-19 1980-04-12 Agency Of Ind Science & Technol Composite element adjusting method by ion beam

Also Published As

Publication number Publication date
GB2001472B (en) 1982-02-17
DE2831523A1 (de) 1979-02-01
IT7825819A0 (it) 1978-07-17
FR2398386A1 (fr) 1979-02-16
GB2001472A (en) 1979-01-31
IT1097967B (it) 1985-08-31
FR2398386B1 (it) 1984-03-23
JPS59112944U (ja) 1984-07-30

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