JPS54968A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS54968A
JPS54968A JP6687777A JP6687777A JPS54968A JP S54968 A JPS54968 A JP S54968A JP 6687777 A JP6687777 A JP 6687777A JP 6687777 A JP6687777 A JP 6687777A JP S54968 A JPS54968 A JP S54968A
Authority
JP
Japan
Prior art keywords
logic circuit
transistors
lowering
establish
increasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6687777A
Other languages
Japanese (ja)
Inventor
Takashi Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6687777A priority Critical patent/JPS54968A/en
Publication of JPS54968A publication Critical patent/JPS54968A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To establish the logic circuit without increasing the number of transistors and lowering in the output voltage due to base bias effect, by providing P or N channel type MOS FET taking clock pulse as the gate input signal.
JP6687777A 1977-06-06 1977-06-06 Logic circuit Pending JPS54968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6687777A JPS54968A (en) 1977-06-06 1977-06-06 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6687777A JPS54968A (en) 1977-06-06 1977-06-06 Logic circuit

Publications (1)

Publication Number Publication Date
JPS54968A true JPS54968A (en) 1979-01-06

Family

ID=13328534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6687777A Pending JPS54968A (en) 1977-06-06 1977-06-06 Logic circuit

Country Status (1)

Country Link
JP (1) JPS54968A (en)

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