JPS5496960A - A-d converter - Google Patents

A-d converter

Info

Publication number
JPS5496960A
JPS5496960A JP340578A JP340578A JPS5496960A JP S5496960 A JPS5496960 A JP S5496960A JP 340578 A JP340578 A JP 340578A JP 340578 A JP340578 A JP 340578A JP S5496960 A JPS5496960 A JP S5496960A
Authority
JP
Japan
Prior art keywords
output
picture frame
analog voltage
add
increment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP340578A
Other languages
Japanese (ja)
Inventor
Hisao Hanmura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP340578A priority Critical patent/JPS5496960A/en
Publication of JPS5496960A publication Critical patent/JPS5496960A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To reduce the scale of the circuit with the high-speed operation as well as to increase the effective resolution by setting the increment of the analog voltage of every picture frame to 1/n the quantization step of the A-D conversion part.
CONSTITUTION: The following units are provided: n-notation counter CNT to count the number of the picture frame; A-D converter DAC to convert the output of CNT into the analog voltage; adder ADD to add the output of DAC to the video signal; and A-D conversion part DEC to convert the output of ADD into the digital value respectively. Then the increment of the analog voltage of every picture frame is set to 1/n the quantization step of DEC. Thus, the number of comparators C1∼C7 can be reduced in spite of the high-speed operation with the enhanced resolution.
COPYRIGHT: (C)1979,JPO&Japio
JP340578A 1978-01-18 1978-01-18 A-d converter Pending JPS5496960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP340578A JPS5496960A (en) 1978-01-18 1978-01-18 A-d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP340578A JPS5496960A (en) 1978-01-18 1978-01-18 A-d converter

Publications (1)

Publication Number Publication Date
JPS5496960A true JPS5496960A (en) 1979-07-31

Family

ID=11556465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP340578A Pending JPS5496960A (en) 1978-01-18 1978-01-18 A-d converter

Country Status (1)

Country Link
JP (1) JPS5496960A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58104577A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device
JPS58104576A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58104577A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device
JPS58104576A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device

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