JPS5499531A - Semiconductor memory unit - Google Patents
Semiconductor memory unitInfo
- Publication number
- JPS5499531A JPS5499531A JP248278A JP248278A JPS5499531A JP S5499531 A JPS5499531 A JP S5499531A JP 248278 A JP248278 A JP 248278A JP 248278 A JP248278 A JP 248278A JP S5499531 A JPS5499531 A JP S5499531A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- drain
- source
- diffusion
- etching process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
Landscapes
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To secure the writing and deletion with the low voltage by providing a single conducting region of a high density around the reverse conducting region inside the substrate and thus to realize both the high integration degree and high performance without increasing the times of the photo etching process. CONSTITUTION:The semiconductor nonvolatile memory element contains n<+> diffusion layer 2 and 2' of the source and drain on P<-> semiconductor substrate 1' of a low impurity density, and P<+> diffusion layer 10 and 10' are formed around layer 2 and 2'. These n<+> and p<+> diffusion layers are formed through the diffusion self- matching via the same aperture part of the source and drain, thus eliminating the extra photo etching process for formation of the p<+> diffusion layer. Furthermore, the p<+> diffusion layer covers not only the drain but the source diffusion layer so that the punch-through phenomenon can be prevented. As a result, the element featuring a small channel length becomes possible easily, realizing a high degree of integration and the high performance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP248278A JPS5499531A (en) | 1978-01-12 | 1978-01-12 | Semiconductor memory unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP248278A JPS5499531A (en) | 1978-01-12 | 1978-01-12 | Semiconductor memory unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5499531A true JPS5499531A (en) | 1979-08-06 |
Family
ID=11530556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP248278A Pending JPS5499531A (en) | 1978-01-12 | 1978-01-12 | Semiconductor memory unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5499531A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5834976A (en) * | 1981-08-26 | 1983-03-01 | Nec Corp | Nonvolatile semiconductor device |
| US5216269A (en) * | 1989-03-31 | 1993-06-01 | U.S. Philips Corp. | Electrically-programmable semiconductor memories with buried injector region |
| US5904518A (en) * | 1988-11-09 | 1999-05-18 | Hitachi, Ltd. | Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells |
-
1978
- 1978-01-12 JP JP248278A patent/JPS5499531A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5834976A (en) * | 1981-08-26 | 1983-03-01 | Nec Corp | Nonvolatile semiconductor device |
| US5904518A (en) * | 1988-11-09 | 1999-05-18 | Hitachi, Ltd. | Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells |
| US6255690B1 (en) | 1988-11-09 | 2001-07-03 | Hitachi, Ltd. | Non-volatile semiconductor memory device |
| US6451643B2 (en) | 1988-11-09 | 2002-09-17 | Hitachi, Ltd. | Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs |
| US6777282B2 (en) | 1988-11-09 | 2004-08-17 | Renesas Technology Corp. | Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs |
| US6960501B2 (en) | 1988-11-09 | 2005-11-01 | Renesas Technology Corp. | Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets |
| US7071050B2 (en) | 1988-11-09 | 2006-07-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having single-element type non-volatile memory elements |
| US7399667B2 (en) | 1988-11-09 | 2008-07-15 | Renesas Technology Corp. | Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements |
| US5216269A (en) * | 1989-03-31 | 1993-06-01 | U.S. Philips Corp. | Electrically-programmable semiconductor memories with buried injector region |
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