JPS5510256A - Binary three-level signal system - Google Patents

Binary three-level signal system

Info

Publication number
JPS5510256A
JPS5510256A JP8318078A JP8318078A JPS5510256A JP S5510256 A JPS5510256 A JP S5510256A JP 8318078 A JP8318078 A JP 8318078A JP 8318078 A JP8318078 A JP 8318078A JP S5510256 A JPS5510256 A JP S5510256A
Authority
JP
Japan
Prior art keywords
signal
level
binary
level signal
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8318078A
Other languages
Japanese (ja)
Inventor
Kimio Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8318078A priority Critical patent/JPS5510256A/en
Publication of JPS5510256A publication Critical patent/JPS5510256A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To simplify operation without using a clock signal, etc., by setting a signal of the 3rd level in addition to a binary signal when recording or inputting binary code information and by allotting the signal of the 3rd level to even-numbered signals when the same binary signals continue. CONSTITUTION:To convert binary code into a three-level signal, a shift to low- level signal L is made when binary code information of ''0'' appears after high- level signal H is outputted and a shift to signal M of the 3rd level differing from the binary signal is made when binary code information of ''1'' appears. When binary code information of ''0'' comes after low-level signal L, a shift to level signal M of the 3rd level is made. When information of ''0'' comes after signal M of the 3rd level, a shift to low-level signal L is made and when information of ''1'', a shift to high-level signal H is made. Then, conversion from binary code information into a three-level signal is carried out easily through automatic of manual operation.
JP8318078A 1978-07-07 1978-07-07 Binary three-level signal system Pending JPS5510256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8318078A JPS5510256A (en) 1978-07-07 1978-07-07 Binary three-level signal system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8318078A JPS5510256A (en) 1978-07-07 1978-07-07 Binary three-level signal system

Publications (1)

Publication Number Publication Date
JPS5510256A true JPS5510256A (en) 1980-01-24

Family

ID=13795092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8318078A Pending JPS5510256A (en) 1978-07-07 1978-07-07 Binary three-level signal system

Country Status (1)

Country Link
JP (1) JPS5510256A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298682A (en) * 1987-05-29 1988-12-06 Nippon Kinsen Kikai Kk bar code
JP2007088776A (en) * 2005-09-21 2007-04-05 Sony Corp Phase information generating apparatus, phase information generating method, transmitter and receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54102811A (en) * 1978-01-20 1979-08-13 Hitachi Ltd Signal system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54102811A (en) * 1978-01-20 1979-08-13 Hitachi Ltd Signal system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298682A (en) * 1987-05-29 1988-12-06 Nippon Kinsen Kikai Kk bar code
JP2007088776A (en) * 2005-09-21 2007-04-05 Sony Corp Phase information generating apparatus, phase information generating method, transmitter and receiver

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