JPS55107366A - Waveform reproduction system - Google Patents

Waveform reproduction system

Info

Publication number
JPS55107366A
JPS55107366A JP1387179A JP1387179A JPS55107366A JP S55107366 A JPS55107366 A JP S55107366A JP 1387179 A JP1387179 A JP 1387179A JP 1387179 A JP1387179 A JP 1387179A JP S55107366 A JPS55107366 A JP S55107366A
Authority
JP
Japan
Prior art keywords
output
latch circuit
latched
read out
threshold value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1387179A
Other languages
Japanese (ja)
Inventor
Shigeyuki Umigami
Kuninosuke Ihira
Keiji Kahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1387179A priority Critical patent/JPS55107366A/en
Publication of JPS55107366A publication Critical patent/JPS55107366A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: To obtain the reproducing data having longer effective processing time and sufficient pulse width accuracy, by suitably interleaving for input and output sampling value and identifying this interval with interpolation through approximate data.
CONSTITUTION: The output pulse of long period interleaved from the digital filter 11 is compared with the threshold value, and the difference is obtained from the subtractor 12 and latched with the clock CLK1 at the latch circuit 13 succeeding. The fixed memory ROM14 is read out by taking the output of the difference of the latch circuit 13 and the output pattern of the discrimination area is picked up. Only when the exclusive logical sum EX-OR detects that the threshold value is exceeded, the latch circuit 15 is latched. The output of the latch circuit 15 is inputted to the parallel serial conversion circuit P/S 16 and the reproduced data is serially read out.
COPYRIGHT: (C)1980,JPO&Japio
JP1387179A 1979-02-09 1979-02-09 Waveform reproduction system Pending JPS55107366A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1387179A JPS55107366A (en) 1979-02-09 1979-02-09 Waveform reproduction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1387179A JPS55107366A (en) 1979-02-09 1979-02-09 Waveform reproduction system

Publications (1)

Publication Number Publication Date
JPS55107366A true JPS55107366A (en) 1980-08-18

Family

ID=11845290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1387179A Pending JPS55107366A (en) 1979-02-09 1979-02-09 Waveform reproduction system

Country Status (1)

Country Link
JP (1) JPS55107366A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57184356A (en) * 1981-05-08 1982-11-13 Seiko Epson Corp Fsk demodulating circuit
JPS57210750A (en) * 1981-06-19 1982-12-24 Fujitsu Ltd Fsk signal demodulating system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57184356A (en) * 1981-05-08 1982-11-13 Seiko Epson Corp Fsk demodulating circuit
JPS57210750A (en) * 1981-06-19 1982-12-24 Fujitsu Ltd Fsk signal demodulating system

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