JPS55123720A - Digital data fetch unit - Google Patents

Digital data fetch unit

Info

Publication number
JPS55123720A
JPS55123720A JP3090379A JP3090379A JPS55123720A JP S55123720 A JPS55123720 A JP S55123720A JP 3090379 A JP3090379 A JP 3090379A JP 3090379 A JP3090379 A JP 3090379A JP S55123720 A JPS55123720 A JP S55123720A
Authority
JP
Japan
Prior art keywords
data
digit
interface
digital
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3090379A
Other languages
Japanese (ja)
Inventor
Yukihiko Inagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idec Corp
Original Assignee
Idec Izumi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idec Izumi Corp filed Critical Idec Izumi Corp
Priority to JP3090379A priority Critical patent/JPS55123720A/en
Publication of JPS55123720A publication Critical patent/JPS55123720A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To process software, which requires two instructions conventionally, with one instruction by operating a digital input module only with the input instruction of a CPU to execute designated digit selection and data read simultaneously.
CONSTITUTION: Digital input module 11 is operated only by the input instruction from a CPU. In case that address selection circuit 12 designates one of digital setting equipments D1WDN according to data on the address bus, a digit of address decoder 13 corresponding to designated digital setting equipment D1 is selected, and common terminal C1 of the D1 digit is connected to the ground level by output interface 14. If the D1 digit of the digital setting equipment is 6, data 0101 appears on data lines B1WB4 and is read by input interface 15. Data output circuit 16 consists of a gate circuit to lead the output signal of interface 15 to the bus line under the selection state of any digit of interface 13 and the output condition of the input instruction. When data is led out to the bus line, setting equipment data is fetched at a timing delayed from the input instruction by T1.
COPYRIGHT: (C)1980,JPO&Japio
JP3090379A 1979-03-15 1979-03-15 Digital data fetch unit Pending JPS55123720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3090379A JPS55123720A (en) 1979-03-15 1979-03-15 Digital data fetch unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3090379A JPS55123720A (en) 1979-03-15 1979-03-15 Digital data fetch unit

Publications (1)

Publication Number Publication Date
JPS55123720A true JPS55123720A (en) 1980-09-24

Family

ID=12316675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3090379A Pending JPS55123720A (en) 1979-03-15 1979-03-15 Digital data fetch unit

Country Status (1)

Country Link
JP (1) JPS55123720A (en)

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