JPS55124251A - Method of fabricating package - Google Patents

Method of fabricating package

Info

Publication number
JPS55124251A
JPS55124251A JP3268979A JP3268979A JPS55124251A JP S55124251 A JPS55124251 A JP S55124251A JP 3268979 A JP3268979 A JP 3268979A JP 3268979 A JP3268979 A JP 3268979A JP S55124251 A JPS55124251 A JP S55124251A
Authority
JP
Japan
Prior art keywords
metal
photosensitive resin
plate
package
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3268979A
Other languages
Japanese (ja)
Inventor
Kenzo Hatada
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3268979A priority Critical patent/JPS55124251A/en
Publication of JPS55124251A publication Critical patent/JPS55124251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/6875—Shapes or dispositions thereof being on a metallic substrate, e.g. insulated metal substrates [IMS]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To reduce the thickness, size and weight of a package by securing a circuit element such as IC or the like into a hole of a light metal substrate insulated on the surface, forming a wiring pattern with photosensitive resin and metal layer and forming a number of wires in high density. CONSTITUTION:An opening 12 is perforated at a metal plate 14 such as aluminum, an insulating film 13 such as Al2O3 or the like if formed on the exposed surface thereof, and active and passive circuit elements 16 such as IC, LSI, resistors, capacitors and the like are secured onto a plate 17 such as aluminum or the like and inserted into the opening 12, and fixed thereto with adhesive resin 18 or the like. Then, photosensitive resin 19 is coated on the entire surface of the plate, electrode portions are perforated, resin except the elements is removed, a metal film 22 is coated then on the entire surface, a photosensitive resin mask 23 is patterned, and necessary wires 24 are formed thereon. Passive elements 15 such as capacitors may be formed on the insulating film. Thus, since the substrate is metal, it can entirely reduce the thickness, size and weight of a package and improve the mechanical strength thereof.
JP3268979A 1979-03-20 1979-03-20 Method of fabricating package Pending JPS55124251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3268979A JPS55124251A (en) 1979-03-20 1979-03-20 Method of fabricating package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3268979A JPS55124251A (en) 1979-03-20 1979-03-20 Method of fabricating package

Publications (1)

Publication Number Publication Date
JPS55124251A true JPS55124251A (en) 1980-09-25

Family

ID=12365824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3268979A Pending JPS55124251A (en) 1979-03-20 1979-03-20 Method of fabricating package

Country Status (1)

Country Link
JP (1) JPS55124251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112888150A (en) * 2021-01-12 2021-06-01 京东方科技集团股份有限公司 Circuit board, display device and wearable device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS482058U (en) * 1971-05-27 1973-01-11
JPS5132755B2 (en) * 1972-06-27 1976-09-14

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS482058U (en) * 1971-05-27 1973-01-11
JPS5132755B2 (en) * 1972-06-27 1976-09-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112888150A (en) * 2021-01-12 2021-06-01 京东方科技集团股份有限公司 Circuit board, display device and wearable device
CN112888150B (en) * 2021-01-12 2022-07-01 京东方科技集团股份有限公司 Circuit board, display device and wearable device

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