JPS55124331A - Bit rate signal generating circuit - Google Patents
Bit rate signal generating circuitInfo
- Publication number
- JPS55124331A JPS55124331A JP3246479A JP3246479A JPS55124331A JP S55124331 A JPS55124331 A JP S55124331A JP 3246479 A JP3246479 A JP 3246479A JP 3246479 A JP3246479 A JP 3246479A JP S55124331 A JPS55124331 A JP S55124331A
- Authority
- JP
- Japan
- Prior art keywords
- bit rate
- clock pulse
- divider counter
- counter
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 101000822028 Homo sapiens Solute carrier family 28 member 3 Proteins 0.000 abstract 2
- 102100021470 Solute carrier family 28 member 3 Human genes 0.000 abstract 2
- 101000685663 Homo sapiens Sodium/nucleoside cotransporter 1 Proteins 0.000 abstract 1
- 102100023116 Sodium/nucleoside cotransporter 1 Human genes 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/15033—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of bistable devices
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To secure the easy supply for the clock pulse of the special bit rate to the data transmitter, by adding the exclusive logic sum gate, the delay circuit and the divider counter each to the counter and the FF which divides the basic clock pulse. CONSTITUTION:Basic clock pulse generator CPG, FF1-7 which are connected vertically to divide the output signals of CPG sequentially down to 1/N (N: integer), divider counter CTN2 plus FF8, 9 are provided to the circuit which generates plural number of bit rate signals of different frequencies. And the outputs of both FF1, 3 among FF1-7 are applied to exclusive logic sum gate G1 via divider counter CNT1. At the same time, the output of G1 is supplied to divider counter CNT3 via the delay circuit which eliminates the noise component. Thus the clock pulse of the special bit rate is generated at the output of CNT3 to be supplied to the data transmitter along with other bit rate pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3246479A JPS55124331A (en) | 1979-03-20 | 1979-03-20 | Bit rate signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3246479A JPS55124331A (en) | 1979-03-20 | 1979-03-20 | Bit rate signal generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55124331A true JPS55124331A (en) | 1980-09-25 |
Family
ID=12359682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3246479A Pending JPS55124331A (en) | 1979-03-20 | 1979-03-20 | Bit rate signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55124331A (en) |
-
1979
- 1979-03-20 JP JP3246479A patent/JPS55124331A/en active Pending
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