JPS55124872A - Noise pattern erase circuit for binary video signal - Google Patents
Noise pattern erase circuit for binary video signalInfo
- Publication number
- JPS55124872A JPS55124872A JP3179879A JP3179879A JPS55124872A JP S55124872 A JPS55124872 A JP S55124872A JP 3179879 A JP3179879 A JP 3179879A JP 3179879 A JP3179879 A JP 3179879A JP S55124872 A JPS55124872 A JP S55124872A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- erase
- point
- video signal
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Image Processing (AREA)
Abstract
PURPOSE:To simplify the circuit constitution, by locating the check point for pattern discrimination under a rule in scattering. CONSTITUTION:From the bit location included in the shift register(N-bit capacity for each row unit shift register) of 10 stage constitution shifting binary video signal sequentially, the bit location P being each group pattern erase point for the check points A0-A3, and check points B(B0, B1), C(C0, C1), D(D0, D1), E(E0, E1) and F(F0, F1), is obtained,and the bit information at bit location obtained is inputted to the erase circuit constituted of AND gates 19-23,25 and OR gate 26, then from the OR gate 26, the bit information relating to the erase or correction of the pattern erase point P is outputted and this is sequentially shifted to the succeeding bit location as the bit information at the pattern erase point P.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3179879A JPS55124872A (en) | 1979-03-20 | 1979-03-20 | Noise pattern erase circuit for binary video signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3179879A JPS55124872A (en) | 1979-03-20 | 1979-03-20 | Noise pattern erase circuit for binary video signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55124872A true JPS55124872A (en) | 1980-09-26 |
| JPS6246900B2 JPS6246900B2 (en) | 1987-10-05 |
Family
ID=12341080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3179879A Granted JPS55124872A (en) | 1979-03-20 | 1979-03-20 | Noise pattern erase circuit for binary video signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55124872A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6086676A (en) * | 1983-10-18 | 1985-05-16 | Nec Corp | Picture signal correcting device |
| JPS60117380A (en) * | 1983-11-30 | 1985-06-24 | Fujitsu Ltd | Pattern processing method |
| CN106339284A (en) * | 2015-07-08 | 2017-01-18 | 想象技术有限公司 | Checkpointing a shift register |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01224599A (en) * | 1988-03-02 | 1989-09-07 | Heiwa Seiki Kogyo Kk | Universal head |
-
1979
- 1979-03-20 JP JP3179879A patent/JPS55124872A/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6086676A (en) * | 1983-10-18 | 1985-05-16 | Nec Corp | Picture signal correcting device |
| JPS60117380A (en) * | 1983-11-30 | 1985-06-24 | Fujitsu Ltd | Pattern processing method |
| CN106339284A (en) * | 2015-07-08 | 2017-01-18 | 想象技术有限公司 | Checkpointing a shift register |
| CN106339284B (en) * | 2015-07-08 | 2021-10-12 | 美普思技术有限责任公司 | Checkpointing shift registers |
| CN113868056A (en) * | 2015-07-08 | 2021-12-31 | 美普思技术有限责任公司 | Checkpointing the shift register |
| CN113868056B (en) * | 2015-07-08 | 2024-11-12 | 美普思技术有限责任公司 | Checkpointing the shift register |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6246900B2 (en) | 1987-10-05 |
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