JPS5513438A - Controller - Google Patents

Controller

Info

Publication number
JPS5513438A
JPS5513438A JP8509878A JP8509878A JPS5513438A JP S5513438 A JPS5513438 A JP S5513438A JP 8509878 A JP8509878 A JP 8509878A JP 8509878 A JP8509878 A JP 8509878A JP S5513438 A JPS5513438 A JP S5513438A
Authority
JP
Japan
Prior art keywords
fault
contents
controller
unit
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8509878A
Other languages
Japanese (ja)
Other versions
JPS6134169B2 (en
Inventor
Takashi Ishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8509878A priority Critical patent/JPS5513438A/en
Publication of JPS5513438A publication Critical patent/JPS5513438A/en
Publication of JPS6134169B2 publication Critical patent/JPS6134169B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To prevent previously the function stop of the whole system caused by the fixed fault within the specified controller by securing an automatic removal of the faulty controller out of the system.
CONSTITUTION: In case some fault is detected within the controller, the fault detection signals (ERR#1, #2...) corresponding to the fault contents are recorded in first fault memory unit 2 under the state of "1". At the same time, the occurrence of the fault is informed to the central controller via fault information signal 9. Second fault memory unit 3 records the contents preceding unit 2, and its contents is cleared by reset signal 4 at time point B after fixed time T. At the occurrence of the fault, the contents is checked between unit 2 and 3 through comparator 5. And if the faults of the same factor occur continuously during time T, connection signal group 7 and 8 are cut off to the central controller via cut-off indication signal 6.
COPYRIGHT: (C)1980,JPO&Japio
JP8509878A 1978-07-14 1978-07-14 Controller Granted JPS5513438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8509878A JPS5513438A (en) 1978-07-14 1978-07-14 Controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8509878A JPS5513438A (en) 1978-07-14 1978-07-14 Controller

Publications (2)

Publication Number Publication Date
JPS5513438A true JPS5513438A (en) 1980-01-30
JPS6134169B2 JPS6134169B2 (en) 1986-08-06

Family

ID=13849126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8509878A Granted JPS5513438A (en) 1978-07-14 1978-07-14 Controller

Country Status (1)

Country Link
JP (1) JPS5513438A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02128233A (en) * 1988-11-09 1990-05-16 Nec Corp Fault processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02147178U (en) * 1989-05-11 1990-12-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02128233A (en) * 1988-11-09 1990-05-16 Nec Corp Fault processor

Also Published As

Publication number Publication date
JPS6134169B2 (en) 1986-08-06

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