JPS5513530A - Data transmission error correcting circuit - Google Patents
Data transmission error correcting circuitInfo
- Publication number
- JPS5513530A JPS5513530A JP8546578A JP8546578A JPS5513530A JP S5513530 A JPS5513530 A JP S5513530A JP 8546578 A JP8546578 A JP 8546578A JP 8546578 A JP8546578 A JP 8546578A JP S5513530 A JPS5513530 A JP S5513530A
- Authority
- JP
- Japan
- Prior art keywords
- signals
- noises
- data transmission
- error correcting
- transmission error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title 1
- 230000003111 delayed effect Effects 0.000 abstract 1
- 230000002194 synthesizing effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To eliminate noise from signals to prevent errors by inputting receiving signals to shift registers and synthesizing delay signals obtained from respective stages. CONSTITUTION:Signals c where noises N1 and N2 are mixed in signals a are inputted to shift registers 2 to 5 and are shifted successively by shift pulse b. In this case, outputs of shift registers are delayed by one-clock components at every stage and have the relation of signals c to f. AND is operated for these signals respectively, and OR is operated for outputs g to i, thereby obtaining signal J where noises are eliminated. Noises can be eliminated when the width of noises is shorter than the period of the shift pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8546578A JPS5513530A (en) | 1978-07-13 | 1978-07-13 | Data transmission error correcting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8546578A JPS5513530A (en) | 1978-07-13 | 1978-07-13 | Data transmission error correcting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5513530A true JPS5513530A (en) | 1980-01-30 |
Family
ID=13859627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8546578A Pending JPS5513530A (en) | 1978-07-13 | 1978-07-13 | Data transmission error correcting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5513530A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62216552A (en) * | 1986-03-18 | 1987-09-24 | Oki Electric Ind Co Ltd | Data receiving circuit |
-
1978
- 1978-07-13 JP JP8546578A patent/JPS5513530A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62216552A (en) * | 1986-03-18 | 1987-09-24 | Oki Electric Ind Co Ltd | Data receiving circuit |
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