JPS55143659A - Memory interface - Google Patents

Abstract

PURPOSE: To quicken the actuation of a memory only by sending addresses, by composing a timing signal from a memory controller to a memory unit of an address-defined timing signal and transfer direction and timing signal of data-transmission.

CONSTITUTION: A request to memory unit 1 is output from arithmetic processor 3 or input-output unit 4 to memory controller 2, which execises selection control and access control over the request to output the request to unit 1. At this time, units 3 and 4, after outputting data to data-transfer-direction indication lines 22 and 27 and data signal lines 25 and 30, outputs memory-start request signals 21 and 26. Receiving those signals 21 and 26, unit 2 selects memory request selective signal 302 by selecting circuit 31 and applies it to interface signal line output circuit 33 and address selecting circuit 32; and circuit 32 outputs address signal 13 of the request side, and circuit 33 address timing signal 311. After checking data, checking circuits 34 and 35 output transfer-direction indication signal 14 and transfer-direction timing signal 313.

COPYRIGHT: (C)1980,JPO&Japio