JPS55146694A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS55146694A JPS55146694A JP3928680A JP3928680A JPS55146694A JP S55146694 A JPS55146694 A JP S55146694A JP 3928680 A JP3928680 A JP 3928680A JP 3928680 A JP3928680 A JP 3928680A JP S55146694 A JPS55146694 A JP S55146694A
- Authority
- JP
- Japan
- Prior art keywords
- refreshing
- read
- digit line
- row
- word line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To eliminate the need to increase electric power capacity for refreshing even when the scale is made larger by providing a sequence control circuit and by refreshing separately with memory cells connecting with a word line several times. CONSTITUTION:Row decoder 2 selects read word line R/W1 and also selects all column-directional read digit lines R/D to transfer information, stored in memory cell MC1, to read digit line R/D1. Then, sequence circuit 4 is put into operation to supply only refreshing circuit 31 with an operating signal and then the information read out to digit line R/D1 is tranferred to digit line W/D1 by selecting write word line W/W1 and digit line W/D1 and then written again in cell MC1. Similarly, memory cell MC2 is refreshed and the refreshing operation is carried on in the row direction sequentially; after the refreshing operation for one row ends, the next row is refreshed, thereby refreshing all memory cells.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3928680A JPS55146694A (en) | 1980-03-27 | 1980-03-27 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3928680A JPS55146694A (en) | 1980-03-27 | 1980-03-27 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55146694A true JPS55146694A (en) | 1980-11-15 |
Family
ID=12548906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3928680A Pending JPS55146694A (en) | 1980-03-27 | 1980-03-27 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55146694A (en) |
-
1980
- 1980-03-27 JP JP3928680A patent/JPS55146694A/en active Pending
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