JPS55149552A - Direct current transmission circuit - Google Patents
Direct current transmission circuitInfo
- Publication number
- JPS55149552A JPS55149552A JP5784079A JP5784079A JPS55149552A JP S55149552 A JPS55149552 A JP S55149552A JP 5784079 A JP5784079 A JP 5784079A JP 5784079 A JP5784079 A JP 5784079A JP S55149552 A JPS55149552 A JP S55149552A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- converter
- pulse width
- waveform
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B14/00—Transmission systems not characterised by the medium used for transmission
- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/026—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse time characteristics modulation, e.g. width, position, interval
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Abstract
PURPOSE:To enable to keep the transmission quality without distortion, by multiplex transmission of two types of DC voltage values or DC current values in time sharing. CONSTITUTION:The DC voltage or current X1, X2 are converted into the pulse wave (a) of pulse width T1=A1X1, T2=A2X2 by the DC-pulse width converter 1 and they are transmitted via the tranmission line L as the optical pulse (b) by the electrooptic converter 2. At the reception section, it is converted into electric signal at the photoelectric converter 3, and as to the pulse T1, the waveform (c) is obtained at the pulse width-peak value converter 5 and the DC signal V01 is obtained at the hold circuit 7. Further, as to the pulse T2, the waveform (e) is obtained at the phase inversion circuit 4, and waveform (f) is obtained at the pulse width- peak value converter 6, and DC signal V02 is obtained at the hold circuit 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54057840A JPS5821463B2 (en) | 1979-05-11 | 1979-05-11 | DC transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54057840A JPS5821463B2 (en) | 1979-05-11 | 1979-05-11 | DC transmission circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55149552A true JPS55149552A (en) | 1980-11-20 |
| JPS5821463B2 JPS5821463B2 (en) | 1983-04-30 |
Family
ID=13067156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54057840A Expired JPS5821463B2 (en) | 1979-05-11 | 1979-05-11 | DC transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821463B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6280665U (en) * | 1985-11-12 | 1987-05-23 |
-
1979
- 1979-05-11 JP JP54057840A patent/JPS5821463B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5821463B2 (en) | 1983-04-30 |
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