JPS5515524A - Digital arithmetic circuit - Google Patents

Digital arithmetic circuit

Info

Publication number
JPS5515524A
JPS5515524A JP8737878A JP8737878A JPS5515524A JP S5515524 A JPS5515524 A JP S5515524A JP 8737878 A JP8737878 A JP 8737878A JP 8737878 A JP8737878 A JP 8737878A JP S5515524 A JPS5515524 A JP S5515524A
Authority
JP
Japan
Prior art keywords
circuit
encoder
output
addition
digital input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8737878A
Other languages
Japanese (ja)
Other versions
JPS5913782B2 (en
Inventor
Akira Fukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8737878A priority Critical patent/JPS5913782B2/en
Publication of JPS5515524A publication Critical patent/JPS5515524A/en
Publication of JPS5913782B2 publication Critical patent/JPS5913782B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To make it possible to execute multiplication and addition in a nearly- equal processing time, by substituting the multiplication, requiring large hardware and a longer arithmetic time in comparison with addition, by addition using logarithms.
CONSTITUTION: The circuit consits of priority encoder 1 which outputs X with the value of a digital input over 2X to 2X+1, priority encoder 1 which outputs X, decoder 2 which expands its output from X, and circuit 3 which obtains OR an'.an-1 of the product as to the same (i) [positive integer] of AND an'.an-1 between the "n"-th output an' of decoder 2 and the "n-1"-th input an-1 of encoder 1. Then, the output of encoder 1 is sent out as the index of the logarithm of the digital input, and that of circuit 3 is as a value of 2-1 digits of the mantissa of the logarithm of the digital input.
COPYRIGHT: (C)1980,JPO&Japio
JP8737878A 1978-07-17 1978-07-17 digital arithmetic circuit Expired JPS5913782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8737878A JPS5913782B2 (en) 1978-07-17 1978-07-17 digital arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8737878A JPS5913782B2 (en) 1978-07-17 1978-07-17 digital arithmetic circuit

Publications (2)

Publication Number Publication Date
JPS5515524A true JPS5515524A (en) 1980-02-02
JPS5913782B2 JPS5913782B2 (en) 1984-03-31

Family

ID=13913226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8737878A Expired JPS5913782B2 (en) 1978-07-17 1978-07-17 digital arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS5913782B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271150A (en) * 1987-04-28 1988-11-09 Osaka Gas Co Ltd Catalytic combustion carbon monoxide gas sensor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0579172U (en) * 1992-03-31 1993-10-26 日本鋼管継手株式会社 Flange pipe fitting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271150A (en) * 1987-04-28 1988-11-09 Osaka Gas Co Ltd Catalytic combustion carbon monoxide gas sensor

Also Published As

Publication number Publication date
JPS5913782B2 (en) 1984-03-31

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