JPS5515528A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS5515528A
JPS5515528A JP8739378A JP8739378A JPS5515528A JP S5515528 A JPS5515528 A JP S5515528A JP 8739378 A JP8739378 A JP 8739378A JP 8739378 A JP8739378 A JP 8739378A JP S5515528 A JPS5515528 A JP S5515528A
Authority
JP
Japan
Prior art keywords
address
microinstruction
routine
microprogram
ffs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8739378A
Other languages
Japanese (ja)
Inventor
Yasuyuki Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8739378A priority Critical patent/JPS5515528A/en
Publication of JPS5515528A publication Critical patent/JPS5515528A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the total number of steps of a microprogram by making it possible to use part of a general microprogram as a subroutine universally.
CONSTITUTION: The processing of the 1st routine advances and in the step where the branch microinstruction of address (m) is stored in microinstruction register R2, address P, the end address of the subroutine, stands by in address stand-by register 7, so that FF10 will be set. Further, change-over circuit 5 selects (n) address 21, a branch-destination address, and performs branching to the 2nd routine. Then, the process of the 2nd routine advances afterward and in the step where the microinstruction of address P is set to R2, FFs 9 and 10 are both set. As a result, the microinstruction of address (m+1) is read out from control memory 1 and then stored in R2, and FFs 9 and 10 are reset to start branching to the 1st routine, thereby continuing the process.
COPYRIGHT: (C)1980,JPO&Japio
JP8739378A 1978-07-17 1978-07-17 Microprogram controller Pending JPS5515528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8739378A JPS5515528A (en) 1978-07-17 1978-07-17 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8739378A JPS5515528A (en) 1978-07-17 1978-07-17 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS5515528A true JPS5515528A (en) 1980-02-02

Family

ID=13913630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8739378A Pending JPS5515528A (en) 1978-07-17 1978-07-17 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS5515528A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831452A (en) * 1981-08-18 1983-02-24 Nec Corp Controlling device for microprogram
JPS5835997U (en) * 1981-08-31 1983-03-09 原　正登 Sewage treatment tank using anti-firestone
JPS59103154A (en) * 1982-12-06 1984-06-14 Nec Corp Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831452A (en) * 1981-08-18 1983-02-24 Nec Corp Controlling device for microprogram
JPS5835997U (en) * 1981-08-31 1983-03-09 原　正登 Sewage treatment tank using anti-firestone
JPS59103154A (en) * 1982-12-06 1984-06-14 Nec Corp Information processor

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