JPS5515542A - Data transmitter - Google Patents

Data transmitter

Info

Publication number
JPS5515542A
JPS5515542A JP8785278A JP8785278A JPS5515542A JP S5515542 A JPS5515542 A JP S5515542A JP 8785278 A JP8785278 A JP 8785278A JP 8785278 A JP8785278 A JP 8785278A JP S5515542 A JPS5515542 A JP S5515542A
Authority
JP
Japan
Prior art keywords
data
bus
processors
data transmitter
reliability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8785278A
Other languages
Japanese (ja)
Other versions
JPS6124739B2 (en
Inventor
Tetsuo Omiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8785278A priority Critical patent/JPS5515542A/en
Publication of JPS5515542A publication Critical patent/JPS5515542A/en
Publication of JPS6124739B2 publication Critical patent/JPS6124739B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)

Abstract

PURPOSE: To obtain a data transmitter available for high-efficiency and high-reliability broadcast communication, by continuing data transmission until a disapproval signal generated when data can not be received is not sent back.
CONSTITUTION: Several processors 31 to 3N are connected in parallel to 1st bus 10 transferring information and 2nd bus 20 transferring a control signal, Processors 31 to 3N function to transmit and receive data via 1st bus 10 and also to send a disapproval signal when data can not be received via 2nd bus 20. For example, when processor 31 sends the same data to all other processors 32 to 3N, resending of the data is continued until the disapproval signal is sent back from all other processors 32 to 2N, so that high-efficiency and high-reliability data transmitter can be realized.
COPYRIGHT: (C)1980,JPO&Japio
JP8785278A 1978-07-18 1978-07-18 Data transmitter Granted JPS5515542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8785278A JPS5515542A (en) 1978-07-18 1978-07-18 Data transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8785278A JPS5515542A (en) 1978-07-18 1978-07-18 Data transmitter

Publications (2)

Publication Number Publication Date
JPS5515542A true JPS5515542A (en) 1980-02-02
JPS6124739B2 JPS6124739B2 (en) 1986-06-12

Family

ID=13926408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8785278A Granted JPS5515542A (en) 1978-07-18 1978-07-18 Data transmitter

Country Status (1)

Country Link
JP (1) JPS5515542A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01109403A (en) * 1987-10-09 1989-04-26 Instron Corp Circuit for interactive control of multiple control elements
JPH02181257A (en) * 1989-01-06 1990-07-16 Hitachi Ltd information processing equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01109403A (en) * 1987-10-09 1989-04-26 Instron Corp Circuit for interactive control of multiple control elements
JPH02181257A (en) * 1989-01-06 1990-07-16 Hitachi Ltd information processing equipment

Also Published As

Publication number Publication date
JPS6124739B2 (en) 1986-06-12

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