JPS55158582A - Electronic clock - Google Patents

Electronic clock

Info

Publication number
JPS55158582A
JPS55158582A JP6637879A JP6637879A JPS55158582A JP S55158582 A JPS55158582 A JP S55158582A JP 6637879 A JP6637879 A JP 6637879A JP 6637879 A JP6637879 A JP 6637879A JP S55158582 A JPS55158582 A JP S55158582A
Authority
JP
Japan
Prior art keywords
stepping motor
power
down counter
output
saving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6637879A
Other languages
Japanese (ja)
Inventor
Kazumitsu Kosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP6637879A priority Critical patent/JPS55158582A/en
Publication of JPS55158582A publication Critical patent/JPS55158582A/en
Pending legal-status Critical Current

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Landscapes

  • Electromechanical Clocks (AREA)

Abstract

PURPOSE: To obtain a power-saving, trouble-free electronic clock by providing the clock with a means for stopping a stepping motor and a means for setting time by quickly rotating the stepping motor when the motor stopping mechanism is released.
CONSTITUTION: An output from a flip-flop 21, which is set by a power-saving switch S1 and reset by a release switch S2, is input into an up-down counter 23. An input pulse to a stepping motor 8 is controlled by an output from a flip-flop 26, which is set by the release switch S2 and reset by an output from a zero detecting circuit 29 in the up-down counter 23. When the power-saving switch S1 is depressed, a driving pulse for the stepping motor 8 is stopped being supplied thereto, and the driving pulse is then supplied to the up-down counter 23. When the release switch S2 is depressed, the stepping motor 8 is quickly rotated in accordance with a counted value in the up-down counter 23. As a result, the time which has elapsed while power is unused is recovered.
COPYRIGHT: (C)1980,JPO&Japio
JP6637879A 1979-05-29 1979-05-29 Electronic clock Pending JPS55158582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6637879A JPS55158582A (en) 1979-05-29 1979-05-29 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6637879A JPS55158582A (en) 1979-05-29 1979-05-29 Electronic clock

Publications (1)

Publication Number Publication Date
JPS55158582A true JPS55158582A (en) 1980-12-10

Family

ID=13314098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6637879A Pending JPS55158582A (en) 1979-05-29 1979-05-29 Electronic clock

Country Status (1)

Country Link
JP (1) JPS55158582A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424600B1 (en) 1998-12-04 2002-07-23 Seiko Epson Corporation Portable electronic device and control method for controlling the portable electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424600B1 (en) 1998-12-04 2002-07-23 Seiko Epson Corporation Portable electronic device and control method for controlling the portable electronic device

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