JPS5516533A - Fm receiver - Google Patents

Fm receiver

Info

Publication number
JPS5516533A
JPS5516533A JP8879478A JP8879478A JPS5516533A JP S5516533 A JPS5516533 A JP S5516533A JP 8879478 A JP8879478 A JP 8879478A JP 8879478 A JP8879478 A JP 8879478A JP S5516533 A JPS5516533 A JP S5516533A
Authority
JP
Japan
Prior art keywords
switch
vco11
supplied
mixer
locking state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8879478A
Other languages
Japanese (ja)
Inventor
Seiichiro Hirata
Yuuji Shiratani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8879478A priority Critical patent/JPS5516533A/en
Publication of JPS5516533A publication Critical patent/JPS5516533A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/26Circuits for superheterodyne receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To capture momentarily a reception frequency assigned by dividing ratio (n) while realizing low-threshold reception by providing a frequency mixer and voltage control oscillator to a FM receiver equipped with a PLL digital frequency synthesizer as a local oscillation circuit. CONSTITUTION:The output of FM demodulator 8 is supplied to VCO11 with switch 12 interposed between its input terminal and earth, and the outputs of VCO11 and VCO41 are supplied to 2nd mixer 10, whose output is supplied to 1st mixer 3. On the bases of whether or not the phase synchronous group of PLL digital synthesizer 4 is in a locking state, the lock detecting method included in phase detector 43 supplies a signal to switch 12, thereby opening and closing switch 12 corresponding to the locking state and unlocking state. With switch 12 opened, the input of VCO11 is therefore fixed to a fixed voltage forcibly.
JP8879478A 1978-07-20 1978-07-20 Fm receiver Pending JPS5516533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8879478A JPS5516533A (en) 1978-07-20 1978-07-20 Fm receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8879478A JPS5516533A (en) 1978-07-20 1978-07-20 Fm receiver

Publications (1)

Publication Number Publication Date
JPS5516533A true JPS5516533A (en) 1980-02-05

Family

ID=13952750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8879478A Pending JPS5516533A (en) 1978-07-20 1978-07-20 Fm receiver

Country Status (1)

Country Link
JP (1) JPS5516533A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245320A (en) * 1984-05-18 1985-12-05 Onkyo Corp Fm receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245320A (en) * 1984-05-18 1985-12-05 Onkyo Corp Fm receiver

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