JPS55165652A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55165652A
JPS55165652A JP7387979A JP7387979A JPS55165652A JP S55165652 A JPS55165652 A JP S55165652A JP 7387979 A JP7387979 A JP 7387979A JP 7387979 A JP7387979 A JP 7387979A JP S55165652 A JPS55165652 A JP S55165652A
Authority
JP
Japan
Prior art keywords
film
wiring
polycrystalline
make
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7387979A
Other languages
Japanese (ja)
Inventor
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP7387979A priority Critical patent/JPS55165652A/en
Publication of JPS55165652A publication Critical patent/JPS55165652A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To surely prevent multilayer wirings from snapping at their edges, shorten wiring intervals and attain a high degree of integration, by utilizing a lift-off method to make the curves of corvers of wiring unsharp. CONSTITUTION:A doped polycrystalline Si film 3 and an Al film 4 are laminated on an SiO2 film on an Si substrate 1 provided with an element. The films 3, 4 are ion-etched under CCl4 gas to make openings 51, 52. The side faces of the polycrystalline Si film 3 are then plasma-etched under CF4 gas to make Al eaves. The SiO2 film is on a hole section of the surface of the substrate is etched. When an Al film 6 is evaporated obliquely downwards, its edges are made unsharp due to the eaves. The polycrystalline Si 3 is removed by CF4 gas plasma etching to provide desired wirings 61, 62. A high-concentration PSG 7 is coated. An opening is made. An Al wiring layer 8 is evaporated for completion. Since dry etching is used except for previous treatment for the Al evaporation and the wiring intervals are greatly shortened by the side face etching, a high degree of integration is enabled and snapping is prevented.
JP7387979A 1979-06-12 1979-06-12 Manufacture of semiconductor device Pending JPS55165652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7387979A JPS55165652A (en) 1979-06-12 1979-06-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7387979A JPS55165652A (en) 1979-06-12 1979-06-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55165652A true JPS55165652A (en) 1980-12-24

Family

ID=13530921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7387979A Pending JPS55165652A (en) 1979-06-12 1979-06-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55165652A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500680A (en) * 1981-05-04 1983-04-28 モトロ−ラ・インコ−ポレ−テツド Semiconductor device with low resistance synthetic metal conductor and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500680A (en) * 1981-05-04 1983-04-28 モトロ−ラ・インコ−ポレ−テツド Semiconductor device with low resistance synthetic metal conductor and method for manufacturing the same

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