JPS55165663A - High-density integrated circuit structure - Google Patents

High-density integrated circuit structure

Info

Publication number
JPS55165663A
JPS55165663A JP7337679A JP7337679A JPS55165663A JP S55165663 A JPS55165663 A JP S55165663A JP 7337679 A JP7337679 A JP 7337679A JP 7337679 A JP7337679 A JP 7337679A JP S55165663 A JPS55165663 A JP S55165663A
Authority
JP
Japan
Prior art keywords
plates
power supply
package
protruded
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7337679A
Other languages
Japanese (ja)
Inventor
Mitsuo Takamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP7337679A priority Critical patent/JPS55165663A/en
Publication of JPS55165663A publication Critical patent/JPS55165663A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To reduce the resistance of power supply lines and ground lines and assure a number of signal contacts without providing multilayer wiring on a laminated ceramic board which constitutes an LSI package, by inserting ground plates and power supply plates into the board so that the plates are protruded from the board and by utilizing the protruded portions of the plates as power supply sections for LSIs. CONSTITUTION:A plurality of LSI elements 6 are placed on the top of an LSI package 1 made of ceramic and are equipped with a protective cover 5. A plurality of contacts 4 are inlaid in the outside of the cover 5. A heat sink 7 is secured on the bottom of the package 1. When the package 1 are provided with power supply plates 2 and ground plates 3, the edges of these plates 2, 3 are protruded from that of the package 1 so that the protruded edges are used as power supply portions for the LSI units 6. The package 1 is thus constituted. The elements 6 are connected to one another through holes 12, 13 perforated on the plates 2, 3. This results in providing power supply lines of low impedance and increasing the mechanical strength.
JP7337679A 1979-06-11 1979-06-11 High-density integrated circuit structure Pending JPS55165663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7337679A JPS55165663A (en) 1979-06-11 1979-06-11 High-density integrated circuit structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7337679A JPS55165663A (en) 1979-06-11 1979-06-11 High-density integrated circuit structure

Publications (1)

Publication Number Publication Date
JPS55165663A true JPS55165663A (en) 1980-12-24

Family

ID=13516394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7337679A Pending JPS55165663A (en) 1979-06-11 1979-06-11 High-density integrated circuit structure

Country Status (1)

Country Link
JP (1) JPS55165663A (en)

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