JPS55165671A - Preparation of semiconductor integrated circuit - Google Patents

Preparation of semiconductor integrated circuit

Info

Publication number
JPS55165671A
JPS55165671A JP7423579A JP7423579A JPS55165671A JP S55165671 A JPS55165671 A JP S55165671A JP 7423579 A JP7423579 A JP 7423579A JP 7423579 A JP7423579 A JP 7423579A JP S55165671 A JPS55165671 A JP S55165671A
Authority
JP
Japan
Prior art keywords
ions
substrate
injected
type
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7423579A
Other languages
Japanese (ja)
Inventor
Masakatsu Yoshida
Atsutomo Toi
Yoshihiko Tochio
Masatoshi Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP7423579A priority Critical patent/JPS55165671A/en
Publication of JPS55165671A publication Critical patent/JPS55165671A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the diffusion time, to enable to treat the device at low temperature and to lessen the production of lattice defect by injecting not only B<+> ions but also Al<+> ions with a high diffusion coefficient into the substrate when a P-type well region is formed in a fixed region of an N-type Si substrate. CONSTITUTION:The N-type Si substrate 1 is coated with SiO2 film 2, the ion injection window 3 is made on a region in which the well is to be formed, and the thin SiO2 film 2' is provided inside of the window 3. Next B<+> ions are injected into the substrate 1 through the thin film 2' while the accelerating energy is regulated so that the quantity of injected ions may be about 2.0X10<12>/cm<2> and Al<+> ions are then injected so that its quantity may be 1X10<14>/cm<2>. After this, the substrate is heat- treated in N2 gas at 900 deg.C for about 30min and further at 1,200 deg.C for about 5hr to ?obtain the P-type well region of ion-injected layer 4. In this way, time for the heat treatment can be reduced to about one fifth as compared with the case of B<+> ions only, and also temperature can be reduced by about 80 deg.C when the time is fixed.
JP7423579A 1979-06-12 1979-06-12 Preparation of semiconductor integrated circuit Pending JPS55165671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7423579A JPS55165671A (en) 1979-06-12 1979-06-12 Preparation of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7423579A JPS55165671A (en) 1979-06-12 1979-06-12 Preparation of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS55165671A true JPS55165671A (en) 1980-12-24

Family

ID=13541294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7423579A Pending JPS55165671A (en) 1979-06-12 1979-06-12 Preparation of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS55165671A (en)

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