JPS5518112A - Analog-digital conversion system - Google Patents

Analog-digital conversion system

Info

Publication number
JPS5518112A
JPS5518112A JP9035978A JP9035978A JPS5518112A JP S5518112 A JPS5518112 A JP S5518112A JP 9035978 A JP9035978 A JP 9035978A JP 9035978 A JP9035978 A JP 9035978A JP S5518112 A JPS5518112 A JP S5518112A
Authority
JP
Japan
Prior art keywords
amplifier
input
gain
level
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9035978A
Other languages
Japanese (ja)
Inventor
Daiki Nabeshima
Yoshitaka Katayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9035978A priority Critical patent/JPS5518112A/en
Publication of JPS5518112A publication Critical patent/JPS5518112A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To avoid the saturation for the output of the amplifier and thus to secure the steady and accurate A/D conversion by minimizing the gain of the amplifier pre- positioned to the A/D converter during decision of the input level.
CONSTITUTION: The A/D converter 22 is pre-positioned with amplifier 21 the gain of which can vary according to the input levels in order to increase the dynamic range. The input is discriminated through level decision circuit 23, and the gain of amplifier 21 is switched via switch 27 in accordance with the output of circuit 23. Now in case the input signal varies at time t1, which region the new input signal is belonging to is decided at time t2. Level "1" is given to latch circuit 25 via awitch 24 in the period of t1∼t2 in order to minimize the gain of amplifier 21. As a rsult, the output of amplifier 21 can be prevented from being saturated with input of the next signal during the level decision.
COPYRIGHT: (C)1980,JPO&Japio
JP9035978A 1978-07-26 1978-07-26 Analog-digital conversion system Pending JPS5518112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9035978A JPS5518112A (en) 1978-07-26 1978-07-26 Analog-digital conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9035978A JPS5518112A (en) 1978-07-26 1978-07-26 Analog-digital conversion system

Publications (1)

Publication Number Publication Date
JPS5518112A true JPS5518112A (en) 1980-02-08

Family

ID=13996330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9035978A Pending JPS5518112A (en) 1978-07-26 1978-07-26 Analog-digital conversion system

Country Status (1)

Country Link
JP (1) JPS5518112A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132021A (en) * 1980-03-19 1981-10-16 Hitachi Ltd Analogue and digital converter
JPH02148917A (en) * 1988-11-29 1990-06-07 Fujikura Ltd Range switching circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132021A (en) * 1980-03-19 1981-10-16 Hitachi Ltd Analogue and digital converter
JPH02148917A (en) * 1988-11-29 1990-06-07 Fujikura Ltd Range switching circuit

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