JPS5518122A - Test system for subscriber circuit - Google Patents
Test system for subscriber circuitInfo
- Publication number
- JPS5518122A JPS5518122A JP9053578A JP9053578A JPS5518122A JP S5518122 A JPS5518122 A JP S5518122A JP 9053578 A JP9053578 A JP 9053578A JP 9053578 A JP9053578 A JP 9053578A JP S5518122 A JPS5518122 A JP S5518122A
- Authority
- JP
- Japan
- Prior art keywords
- test
- faulty
- tester
- result
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
- H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9053578A JPS5518122A (en) | 1978-07-26 | 1978-07-26 | Test system for subscriber circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9053578A JPS5518122A (en) | 1978-07-26 | 1978-07-26 | Test system for subscriber circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5518122A true JPS5518122A (en) | 1980-02-08 |
Family
ID=14001096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9053578A Pending JPS5518122A (en) | 1978-07-26 | 1978-07-26 | Test system for subscriber circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5518122A (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59141861A (ja) * | 1983-02-01 | 1984-08-14 | Nec Corp | 加入者線試験方式 |
-
1978
- 1978-07-26 JP JP9053578A patent/JPS5518122A/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59141861A (ja) * | 1983-02-01 | 1984-08-14 | Nec Corp | 加入者線試験方式 |
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