JPS5518725A - Information control system - Google Patents

Information control system

Info

Publication number
JPS5518725A
JPS5518725A JP9030078A JP9030078A JPS5518725A JP S5518725 A JPS5518725 A JP S5518725A JP 9030078 A JP9030078 A JP 9030078A JP 9030078 A JP9030078 A JP 9030078A JP S5518725 A JPS5518725 A JP S5518725A
Authority
JP
Japan
Prior art keywords
signal
selective
signal line
gate
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9030078A
Other languages
Japanese (ja)
Other versions
JPS5756736B2 (en
Inventor
Kiyoo Moroto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9030078A priority Critical patent/JPS5518725A/en
Publication of JPS5518725A publication Critical patent/JPS5518725A/en
Publication of JPS5756736B2 publication Critical patent/JPS5756736B2/ja
Granted legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To make it possible to check definitely whether double delection should be made or not, by inhibiting any unit from sending an interruption signal while the controller of an information control system is sending selective signal out.
CONSTITUTION: Controller 1, when selecting one of units 2 to 4, sends an address out to interface line 8. This address is simultaneously sent out to interface circuits 5 of units 2 to 4. Each circuit 5 collates the sent address with its own unit number and in case of a coincidence, selective coincidence signal line 11 changes into "1". Selective signal line 12 is normally "1" and when no selective signal is sent, the interruption signal of interruption signal line 13 is sent out to signal line 9 by way of AND gate 7 and OR gate 6. However, once the selective signal is sent out from controller 1, selective signal line 12 changes into "0" to turn AND gate 7 OFF, thereby inhibiting the transmission of the interruption signal to signal line 9.
COPYRIGHT: (C)1980,JPO&Japio
JP9030078A 1978-07-24 1978-07-24 Information control system Granted JPS5518725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9030078A JPS5518725A (en) 1978-07-24 1978-07-24 Information control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9030078A JPS5518725A (en) 1978-07-24 1978-07-24 Information control system

Publications (2)

Publication Number Publication Date
JPS5518725A true JPS5518725A (en) 1980-02-09
JPS5756736B2 JPS5756736B2 (en) 1982-12-01

Family

ID=13994678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9030078A Granted JPS5518725A (en) 1978-07-24 1978-07-24 Information control system

Country Status (1)

Country Link
JP (1) JPS5518725A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132889U (en) * 1984-02-16 1985-09-05 株式会社　カネロン masking tape
JPS61136462A (en) * 1984-12-05 1986-06-24 Kowa Kagaku Kogyo Kk Masking method
JPH0394969U (en) * 1990-01-08 1991-09-27

Also Published As

Publication number Publication date
JPS5756736B2 (en) 1982-12-01

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