JPS5520065A - Synchronizing separator circuit for television picture receiver - Google Patents

Synchronizing separator circuit for television picture receiver

Info

Publication number
JPS5520065A
JPS5520065A JP9340878A JP9340878A JPS5520065A JP S5520065 A JPS5520065 A JP S5520065A JP 9340878 A JP9340878 A JP 9340878A JP 9340878 A JP9340878 A JP 9340878A JP S5520065 A JPS5520065 A JP S5520065A
Authority
JP
Japan
Prior art keywords
capacitor
resistance
base
earthed
via resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9340878A
Other languages
Japanese (ja)
Inventor
Tsuneo Tateshimo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9340878A priority Critical patent/JPS5520065A/en
Publication of JPS5520065A publication Critical patent/JPS5520065A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Picture Signal Circuits (AREA)

Abstract

PURPOSE: To obtain the steady vertical synchronizing performance even when the ghost wave is received by lowering previously the clip level only at the vertical synchronous signal part.
CONSTITUTION: Input terminal 1 is connected to the base of transistor T1 via resistance R1 and capacitor C1 in series, and the base is connected to the +B power source via resistance R2. The collector is connected to the +B power source via resistance R3 as well as to output terminal 2. While terminal 1 is set parallel to the circuit and then connected to the base of transistor T2 via resistance R4 and capacitor C3 in series, and the collector is connected to the emitter of T1 as well as earthed via forward diode D1 with the emitter also earthed. At the same time, the joint of R4 and C3 is earthed via capacitor C2, and resistance R5 is connected in parallel to C3. In such way, the clip level is varied automatically at the vartical synchronous part, thus securing the steady synchronizing separation.
COPYRIGHT: (C)1980,JPO&Japio
JP9340878A 1978-07-31 1978-07-31 Synchronizing separator circuit for television picture receiver Pending JPS5520065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9340878A JPS5520065A (en) 1978-07-31 1978-07-31 Synchronizing separator circuit for television picture receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9340878A JPS5520065A (en) 1978-07-31 1978-07-31 Synchronizing separator circuit for television picture receiver

Publications (1)

Publication Number Publication Date
JPS5520065A true JPS5520065A (en) 1980-02-13

Family

ID=14081463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9340878A Pending JPS5520065A (en) 1978-07-31 1978-07-31 Synchronizing separator circuit for television picture receiver

Country Status (1)

Country Link
JP (1) JPS5520065A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57174739U (en) * 1981-04-28 1982-11-04

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57174739U (en) * 1981-04-28 1982-11-04

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