JPS5520507A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5520507A
JPS5520507A JP7913578A JP7913578A JPS5520507A JP S5520507 A JPS5520507 A JP S5520507A JP 7913578 A JP7913578 A JP 7913578A JP 7913578 A JP7913578 A JP 7913578A JP S5520507 A JPS5520507 A JP S5520507A
Authority
JP
Japan
Prior art keywords
unit
bus
wsvi
master
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7913578A
Other languages
Japanese (ja)
Inventor
Tetsunori Nishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP7913578A priority Critical patent/JPS5520507A/en
Publication of JPS5520507A publication Critical patent/JPS5520507A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To reduce the time loss due to queuing, in the case of bidirectional information transfer between master and slave.
CONSTITUTION: When the information transfer is made via the bus connection unit 5 between the processors 3-0,... at the bus line 1 and the processor 4 at the second bus line 2, when data write-in is made to 3-0 as the master and to 4 as the slave, the unit 5 knows the presence of the master at the line 1 but can not know whether the operation is the data write or data read. The control section 6 at the unit 5 makes the signal S1 to 1, 3-0 feeds ADRS and DATA on the respective bus and delivers the site service-in signal WSvi also. The AND circuit 9 is turned on and 11 is also turned on, and the two sets of information are fed to the unit 4. The WSVi(A) produced after time T is delivered as it is on the bus 2 in the timing received at the unit 5 as WSVi(A)' as it is, and no time delay is caused.
COPYRIGHT: (C)1980,JPO&Japio
JP7913578A 1978-06-29 1978-06-29 Data transfer system Pending JPS5520507A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7913578A JPS5520507A (en) 1978-06-29 1978-06-29 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7913578A JPS5520507A (en) 1978-06-29 1978-06-29 Data transfer system

Publications (1)

Publication Number Publication Date
JPS5520507A true JPS5520507A (en) 1980-02-14

Family

ID=13681502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7913578A Pending JPS5520507A (en) 1978-06-29 1978-06-29 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5520507A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886096A (en) * 1996-09-06 1999-03-23 Unitika Ltd. Polyamide resin composition, and fibers, films and molded articles using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886096A (en) * 1996-09-06 1999-03-23 Unitika Ltd. Polyamide resin composition, and fibers, films and molded articles using the same

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